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/openbmc/qemu/hw/i3c/
H A Dremote-i3c.c2 * Remote I3C Device
23 #include "hw/i3c/i3c.h"
24 #include "hw/i3c/remote-i3c.h"
68 RemoteI3C *i3c = REMOTE_I3C(t); in remote_i3c_recv() local
72 qemu_chr_fe_write_all(&i3c->chr, &type, 1); in remote_i3c_recv()
74 qemu_chr_fe_write_all(&i3c->chr, (uint8_t *)&num_to_read_le, in remote_i3c_recv()
79 qemu_chr_fe_read_all(&i3c->chr, (uint8_t *)&num_read, sizeof(num_read)); in remote_i3c_recv()
82 qemu_chr_fe_read_all(&i3c->chr, data, num_read); in remote_i3c_recv()
83 trace_remote_i3c_recv(i3c->cfg.name, num_read, num_to_read); in remote_i3c_recv()
87 static inline bool remote_i3c_tx_in_progress(RemoteI3C *i3c) in remote_i3c_tx_in_progress() argument
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H A Dtrace-events4 aspeed_i3c_read(uint64_t offset, uint64_t data) "I3C read: offset 0x%" PRIx64 " data 0x%" PRIx64
5 aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64
6 aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset…
7 aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offs…
8 aspeed_i3c_device_send(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] send %" PRId32 " bytes t…
9 aspeed_i3c_device_recv_data(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] recv %" PRId32 " by…
10 aspeed_i3c_device_ibi_recv(uint32_t deviceid, uint8_t ibi_byte) "I3C Dev[%u] recv IBI byte 0x%" PRI…
11 aspeed_i3c_device_ibi_handle(uint32_t deviceid, uint8_t addr, bool rnw) "I3C Dev[%u] handle IBI fro…
12 aspeed_i3c_device_reset(uint32_t deviceid) "I3C Dev[%u] reset"
13 aspeed_i3c_device_pop_rx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] pop 0x%" PRIx32 " from RX F…
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H A Dmock-target.c2 * Mock I3C Device
6 * The mock I3C device can be thought of as a simple EEPROM. It has a buffer,
7 * and the pointer in the buffer is reset to 0 on an I3C STOP.
16 * It also supports a handful of CCCs that are typically used when probing I3C
33 #include "hw/i3c/i3c.h"
34 #include "hw/i3c/mock-target.h"
53 static uint32_t mock_target_rx(I3CTarget *i3c, uint8_t *data, in mock_target_rx() argument
56 MockTargetState *s = MOCK_TARGET(i3c); in mock_target_rx()
83 static int mock_target_tx(I3CTarget *i3c, const uint8_t *data, in mock_target_tx() argument
86 MockTargetState *s = MOCK_TARGET(i3c); in mock_target_tx()
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H A DKconfig1 config I3C config
5 # Device group for i3c devices which can reasonably be user-plugged to any
6 # board's i3c bus.
11 select I3C
16 select I3C
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-i3c1 What: /sys/bus/i3c/devices/i3c-<bus-id>
3 Contact: linux-i3c@vger.kernel.org
5 An I3C bus. This directory will contain one sub-directory per
6 I3C device present on the bus.
8 What: /sys/bus/i3c/devices/i3c-<bus-id>/current_master
10 Contact: linux-i3c@vger.kernel.org
17 What: /sys/bus/i3c/devices/i3c-<bus-id>/mode
19 Contact: linux-i3c@vger.kernel.org
21 I3C bus mode. Can be "pure", "mixed-fast" or "mixed-slow". See
22 the I3C specification for a detailed description of what each
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/openbmc/linux/include/linux/i3c/
H A Dmaster.h15 #include <linux/i3c/ccc.h>
16 #include <linux/i3c/device.h>
38 * struct i3c_i2c_dev_desc - Common part of the I3C/I2C device descriptor
39 * @node: node element used to insert the slot into the I2C or I3C device
41 * @master: I3C master that instantiated this device. Will be used to do
42 * I2C/I3C transfers
46 * This structure is describing common I3C/I2C dev information.
64 * @lvr: LVR (Legacy Virtual Register) needed by the I3C core to know about
68 * Each I2C device connected on the I3C bus should have one.
82 * @lvr: LVR (Legacy Virtual Register) needed by the I3C core to know about
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H A Ddevice.h19 * enum i3c_error_code - I3C error codes
21 * @I3C_ERROR_UNKNOWN: unknown error, usually means the error is not I3C
27 * These are the standard error codes as defined by the I3C specification.
54 * struct i3c_priv_xfer - I3C SDR private transfer
61 * @err: I3C error code
75 * enum i3c_dcr - I3C DCR values
76 * @I3C_DCR_GENERIC_DEVICE: generic I3C device
100 * struct i3c_device_info - I3C device information
114 * These are all basic information that should be advertised by an I3C device.
117 * For each I3C slave attached to a master with
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/openbmc/linux/drivers/i3c/master/
H A DKconfig3 tristate "Cadence I3C master driver"
4 depends on I3C
8 Enable this driver if you want to support Cadence I3C master block.
11 tristate "Synospsys DesignWare I3C master driver"
12 depends on I3C
17 Support for Synopsys DesignWare MIPI I3C Controller.
23 will be called dw-i3c-master.
26 tristate "ASPEED AST2600 I3C master driver"
31 Support for ASPEED AST2600 I3C Controller.
33 This hardware is an instance of the DW I3C controller; this
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H A Dast2600-i3c-master.c14 #include "dw-i3c-master.h"
79 struct ast2600_i3c *i3c = to_ast2600_i3c(dw); in ast2600_i3c_init() local
84 rc = ast2600_i3c_pullup_to_reg(i3c->sda_pullup, &reg); in ast2600_i3c_init()
88 rc = regmap_write(i3c->global_regs, in ast2600_i3c_init()
89 AST2600_I3CG_REG0(i3c->global_idx), reg); in ast2600_i3c_init()
96 reg = AST2600_I3CG_REG1_INST_ID(i3c->global_idx); in ast2600_i3c_init()
97 rc = regmap_write(i3c->global_regs, in ast2600_i3c_init()
98 AST2600_I3CG_REG1(i3c->global_idx), reg); in ast2600_i3c_init()
103 static void ast2600_i3c_set_dat_ibi(struct dw_i3c_master *i3c, in ast2600_i3c_set_dat_ibi() argument
108 * The ast2600 i3c controller will lock up on receiving 4n+1-byte IBIs in ast2600_i3c_set_dat_ibi()
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/openbmc/linux/Documentation/driver-api/i3c/
H A Dprotocol.rst4 I3C protocol
12 collisions are prevented, ...) please have a look at the I3C specification.
14 This document is just a brief introduction to the I3C protocol and the concepts
16 I3C specification (can be downloaded here
17 https://resources.mipi.org/mipi-i3c-v1-download).
22 The I3C (pronounced 'eye-three-see') is a MIPI standardized protocol designed
27 I3C Bus
30 An I3C bus is made of several I3C devices and possibly some I2C devices as
31 well, but let's focus on I3C devices for now.
33 An I3C device on the I3C bus can have one of the following roles:
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/openbmc/linux/Documentation/devicetree/bindings/i3c/
H A Di3c.yaml4 $id: http://devicetree.org/schemas/i3c/i3c.yaml#
7 title: I3C bus
14 I3C busses can be described with a node for the primary I3C controller device
15 and a set of child nodes for each I2C or I3C slave on the bus. Each of them
20 pattern: "^i3c-master@[0-9a-f]+$"
27 All I3C devices are supposed to support DAA (Dynamic Address Assignment),
28 and are thus discoverable. So, by default, I3C devices do not have to be
32 I3C devices.
34 Another use case for describing an I3C device in the device tree is when
35 this I3C device has a static I2C address and we want to assign it a
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H A Dmipi-i3c-hci.yaml4 $id: http://devicetree.org/schemas/i3c/mipi-i3c-hci.yaml#
7 title: MIPI I3C HCI
13 - $ref: /schemas/i3c/i3c.yaml#
16 MIPI I3C Host Controller Interface
18 The MIPI I3C HCI (Host Controller Interface) specification defines
19 a common software driver interface to support compliant MIPI I3C
27 https://www.mipi.org/specifications/i3c-hci
31 const: mipi-i3c-hci
46 i3c-master@a0000000 {
47 compatible = "mipi-i3c-hci";
H A Daspeed,ast2600-i3c.yaml4 $id: http://devicetree.org/schemas/i3c/aspeed,ast2600-i3c.yaml#
7 title: ASPEED AST2600 i3c controller
13 - $ref: i3c.yaml#
17 const: aspeed,ast2600-i3c
41 - description: phandle to i3c global register syscon node
42 - description: index of this i3c controller in the global register set
44 A (phandle, controller index) reference to the i3c global register set
60 i3c-master@2000 {
61 compatible = "aspeed,ast2600-i3c";
H A Dsnps,dw-i3c-master.yaml4 $id: http://devicetree.org/schemas/i3c/snps,dw-i3c-master.yaml#
7 title: Synopsys DesignWare I3C master block
13 - $ref: i3c.yaml#
17 const: snps,dw-i3c-master-1.00a
38 i3c-master@2000 {
39 compatible = "snps,dw-i3c-master-1.00a";
H A Dcdns,i3c-master.yaml4 $id: http://devicetree.org/schemas/i3c/cdns,i3c-master.yaml#
7 title: Cadence I3C master block
13 - $ref: i3c.yaml#
17 const: cdns,i3c-master
44 i3c-master@d040000 {
45 compatible = "cdns,i3c-master";
H A Dsilvaco,i3c-master.yaml4 $id: http://devicetree.org/schemas/i3c/silvaco,i3c-master.yaml#
7 title: Silvaco I3C master
13 - $ref: i3c.yaml#
17 const: silvaco,i3c-master-v1
51 i3c-master@a0000000 {
52 compatible = "silvaco,i3c-master-v1";
/openbmc/linux/drivers/i3c/
H A DKconfig3 menuconfig I3C config
4 tristate "I3C support"
7 I3C is a serial protocol standardized by the MIPI alliance.
13 The I3C protocol also standardizes the slave device types and is
16 If you want I3C support, you should say Y here and also to the
19 This I3C support can also be built as a module. If so, the module
20 will be called i3c.
22 if I3C
23 source "drivers/i3c/master/Kconfig"
24 endif # I3C
/openbmc/openbmc/meta-facebook/meta-yosemite4/recipes-phosphor/state/phosphor-state-manager/
H A Dcheck-i3c-hub27 hub_path="/sys/kernel/debug/i3c-hub-0-*/reg"
28 i3c_hub_lock="/tmp/i3c-hub0.lock"
29 echo "Slot$target_slot on i3c hub 0."
31 hub_path="/sys/kernel/debug/i3c-hub-1-*/reg"
32 i3c_hub_lock="/tmp/i3c-hub1.lock"
33 echo "Slot$target_slot on i3c hub 1."
46 echo "Unlock i3c hub register."
50 echo "Check slot${target_slot} i3c port."
62 echo "Enable slot${target_slot} i3c port."
70 echo "Disable slot${target_slot} i3c port."
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H A Dchassis-poweroff35 echo "Do 12V off disable i3c hub"
37 hub_path="/sys/kernel/debug/i3c-hub-0-*/reg"
38 i3c_hub_lock="/tmp/i3c-hub0.lock"
39 echo "Slot$target_slot on i3c hub 0."
41 hub_path="/sys/kernel/debug/i3c-hub-1-*/reg"
42 i3c_hub_lock="/tmp/i3c-hub1.lock"
43 echo "Slot$target_slot on i3c hub 1."
56 echo "Unlock i3c hub register."
60 echo "Disable slot${target_slot} i3c port."
72 echo "Lock i3c hub register."
/openbmc/linux/drivers/net/mctp/
H A Dmctp-i3c.c4 * "DSP0233 Management Component Transport Protocol (MCTP) I3C Transport
13 #include <linux/i3c/device.h>
14 #include <linux/i3c/master.h>
73 struct i3c_device *i3c; member
82 /* I3C dynamic address */
128 rc = i3c_device_do_priv_xfers(mi->i3c, &xfer, 1); in mctp_i3c_read()
133 /* Bad i3c bus driver */ in mctp_i3c_read()
175 static void mctp_i3c_ibi_handler(struct i3c_device *i3c, in mctp_i3c_ibi_handler() argument
178 struct mctp_i3c_device *mi = i3cdev_get_drvdata(i3c); in mctp_i3c_ibi_handler()
186 /* Not a mctp-i3c interrupt, ignore it */ in mctp_i3c_ibi_handler()
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/openbmc/linux/drivers/base/regmap/
H A Dregmap-i3c.c5 #include <linux/i3c/device.h>
6 #include <linux/i3c/master.h>
12 struct i3c_device *i3c = dev_to_i3cdev(dev); in regmap_i3c_write() local
21 return i3c_device_do_priv_xfers(i3c, xfers, 1); in regmap_i3c_write()
29 struct i3c_device *i3c = dev_to_i3cdev(dev); in regmap_i3c_read() local
40 return i3c_device_do_priv_xfers(i3c, xfers, 2); in regmap_i3c_read()
48 struct regmap *__devm_regmap_init_i3c(struct i3c_device *i3c, in __devm_regmap_init_i3c() argument
53 return __devm_regmap_init(&i3c->dev, &regmap_i3c, &i3c->dev, config, in __devm_regmap_init_i3c()
59 MODULE_DESCRIPTION("Regmap I3C Module");
/openbmc/openbmc/meta-facebook/meta-yosemite4/recipes-phosphor/gpio/phosphor-gpio-monitor/
H A Ddisable-i3c-hub14 hub_path="/sys/kernel/debug/i3c-hub-0-*/reg"
15 i3c_hub_lock="/tmp/i3c-hub0.lock"
16 echo "Slot $unplugged_slot on i3c hub 0."
18 hub_path="/sys/kernel/debug/i3c-hub-1-*/reg"
19 i3c_hub_lock="/tmp/i3c-hub1.lock"
20 echo "Slot $unplugged_slot on i3c hub 1."
33 echo "Unlock i3c hub register."
37 echo "Disable slot${unplugged_slot} i3c port."
48 echo "Lock i3c hub register."
H A Den-i3c-hub-scan-fru15 echo "Do 12V on enable i3c-hub"
18 hub_path="/sys/kernel/debug/i3c-hub-0-*/reg"
19 i3c_hub_lock="/tmp/i3c-hub0.lock"
20 echo "Slot${target_slot} on i3c hub 0."
22 hub_path="/sys/kernel/debug/i3c-hub-1-*/reg"
23 i3c_hub_lock="/tmp/i3c-hub1.lock"
24 echo "Slot${target_slot} on i3c hub 1."
37 echo "Unlock i3c hub register."
41 echo "Enable slot${target_slot} i3c port."
52 echo "Lock i3c hub register."
/openbmc/qemu/include/hw/i3c/
H A Di3c.h2 * QEMU I3C bus interface.
24 #define TYPE_I3C_TARGET "i3c-target"
111 * Target to controller. I3C targets are able to terminate reads early, so
119 * CCCs are I3C commands that I3C targets support.
126 * CCCs are I3C commands that I3C targets support.
157 #define TYPE_I3C_BUS "i3c-bus"
193 * Start a transfer on an I3C bus.
203 * Start a receive transfer on an I3C bus.
210 * Start a send transfer on an I3C bus.
222 * I3C receives can only NACK on a CCC. The target should NACK a CCC it does not
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H A Dmock-target.h5 * Mock I3C Device
9 * The mock I3C device can be thought of as a simple EEPROM. It has a buffer,
10 * and the pointer in the buffer is reset to 0 on an I3C STOP.
19 * It also supports a handful of CCCs that are typically used when probing I3C
35 #include "hw/i3c/i3c.h"
41 I3CTarget i3c; member

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