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/openbmc/u-boot/drivers/sound/
H A Dbroadwell_i2s.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Intel Broadwell I2S driver
7 * Modified from dc i2s/broadwell/broadwell.c
14 #include <i2s.h>
29 uint sclk_dummy_stop; /* 0-31 */
30 uint sclk_frame_width; /* 1-38 */
32 struct broadwell_i2s_regs *regs; member
43 clrsetbits_le32(&priv->shim->csr, in init_shim_csr()
54 u32 clkctl = readl(&priv->shim->clkctl); in init_shim_clkctl()
61 if (uc_priv->id) in init_shim_clkctl()
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H A Drockchip_i2s.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Taken from dc i2s/rockchip.c
12 #include <i2s.h>
51 struct rk_i2s_regs *regs = (struct rk_i2s_regs *)priv->base_address; in rockchip_i2s_init() local
52 u32 bps = priv->bitspersample; in rockchip_i2s_init()
53 u32 lrf = priv->rfs; in rockchip_i2s_init()
54 u32 chn = priv->channels; in rockchip_i2s_init()
57 clrbits_le32(&regs->xfer, I2S_TX_TRAN_BIT); in rockchip_i2s_init()
58 mode = readl(&regs->txcr) & ~0x1f; in rockchip_i2s_init()
59 switch (priv->bitspersample) { in rockchip_i2s_init()
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H A Drt5677.c1 // SPDX-License-Identifier: GPL-2.0+
18 /* RT5677 has 256 8-bit register addresses, and 16-bit register data */
49 * rt5677_i2c_read() - Read a 16-bit register
53 * @returns data read or -ve on error
60 ret = dm_i2c_read(priv->dev, reg, buf, sizeof(u16)); in rt5677_i2c_read()
67 * rt5677_i2c_write() - Write a 16-bit register
72 * @returns 0 if OK, -ve on error
81 return dm_i2c_write(priv->dev, reg, buf, sizeof(u16)); in rt5677_i2c_write()
85 * rt5677_bic_or() - Set and clear bits of a codec register
91 * @returns 0 if OK, -ve on error
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H A Dsamsung-i2s.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <i2s.h>
13 #include <asm/arch/i2s-regs.h>
22 #define TIMEOUT_I2S_TX 100 /* i2s transfer timeout */
25 * Sets the frame size for I2S LR clock
27 * @param i2s_reg i2s register address
32 unsigned int mod = readl(&i2s_reg->mod); in i2s_set_lr_framesize()
51 writel(mod, &i2s_reg->mod); in i2s_set_lr_framesize()
55 * Sets the i2s transfer control
57 * @param i2s_reg i2s register address
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/openbmc/linux/sound/soc/xtensa/
H A Dxtfpga-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Xtfpga I2S controller driver
17 #define DRV_NAME "xtfpga-i2s"
46 * I2S controller operation:
61 void __iomem *regs; member
69 * read-side critical section. Trigger callback sets and clears the
76 unsigned (*tx_fn)(struct xtfpga_i2s *i2s,
123 * xtfpga_pcm_tx_2x16 for 16-bit stereo.
125 * FIFO consists of 32-bit words, one word per channel, always 2 channels.
126 * If I2S interface is configured with smaller sample resolution, only
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/openbmc/linux/sound/soc/meson/
H A Dg12a-tohdmitx.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <sound/soc-dai.h>
15 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
16 #include "meson-codec-glue.h"
18 #define G12A_TOHDMITX_DRV_NAME "g12a-tohdmitx"
35 "I2S A", "I2S B", "I2S C",
45 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in g12a_tohdmitx_i2s_mux_put_enum()
48 if (ucontrol->value.enumerated.item[0] >= e->items) in g12a_tohdmitx_i2s_mux_put_enum()
49 return -EINVAL; in g12a_tohdmitx_i2s_mux_put_enum()
51 mux = snd_soc_enum_item_to_val(e, ucontrol->value.enumerated.item[0]); in g12a_tohdmitx_i2s_mux_put_enum()
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H A Daiu.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <sound/soc-dai.h>
15 #include <dt-bindings/sound/meson-aiu.h>
17 #include "aiu-fifo.h"
22 "SPDIF", "I2S",
38 { "I2S Encoder Playback", NULL, "I2S FIFO Playback" },
40 { "SPDIF SRC SEL", "I2S", "I2S FIFO Playback" },
52 if (args->args_count != 2) in aiu_of_xlate_dai_name()
53 return -EINVAL; in aiu_of_xlate_dai_name()
55 if (args->args[0] != component_id) in aiu_of_xlate_dai_name()
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H A Dg12a-toacodec.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <sound/soc-dai.h>
16 #include <dt-bindings/sound/meson-g12a-toacodec.h>
17 #include "axg-tdm.h"
18 #include "meson-codec-glue.h"
20 #define G12A_TOACODEC_DRV_NAME "g12a-toacodec"
60 "I2S A", "I2S B", "I2S C",
71 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in g12a_toacodec_mux_put_enum()
74 if (ucontrol->value.enumerated.item[0] >= e->items) in g12a_toacodec_mux_put_enum()
75 return -EINVAL; in g12a_toacodec_mux_put_enum()
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/openbmc/linux/sound/soc/tegra/
H A Dtegra20_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * tegra20_i2s.c - Tegra20 I2S driver
6 * Copyright (C) 2010,2012 - NVIDIA, Inc.
10 * Copyright (c) 2009-2010, NVIDIA Corporation.
35 #define DRV_NAME "tegra20-i2s"
39 struct tegra20_i2s *i2s = dev_get_drvdata(dev); in tegra20_i2s_runtime_suspend() local
41 regcache_cache_only(i2s->regmap, true); in tegra20_i2s_runtime_suspend()
43 clk_disable_unprepare(i2s->clk_i2s); in tegra20_i2s_runtime_suspend()
50 struct tegra20_i2s *i2s = dev_get_drvdata(dev); in tegra20_i2s_runtime_resume() local
53 ret = reset_control_assert(i2s->reset); in tegra20_i2s_runtime_resume()
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H A Dtegra30_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * tegra30_i2s.c - Tegra30 I2S driver
6 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
10 * Copyright (c) 2009-2010, NVIDIA Corporation.
37 #define DRV_NAME "tegra30-i2s"
41 struct tegra30_i2s *i2s = dev_get_drvdata(dev); in tegra30_i2s_runtime_suspend() local
43 regcache_cache_only(i2s->regmap, true); in tegra30_i2s_runtime_suspend()
45 clk_disable_unprepare(i2s->clk_i2s); in tegra30_i2s_runtime_suspend()
52 struct tegra30_i2s *i2s = dev_get_drvdata(dev); in tegra30_i2s_runtime_resume() local
55 ret = clk_prepare_enable(i2s->clk_i2s); in tegra30_i2s_runtime_resume()
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H A Dtegra210_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra210_i2s.c - Tegra210 I2S driver
31 * is required to select i2s4b for it to be functional for I2S
42 regmap_write(regmap, TEGRA210_I2S_SLOT_CTRL, total_slots - 1); in tegra210_i2s_set_slot_ctrl()
50 struct tegra210_i2s *i2s = dev_get_drvdata(dev); in tegra210_i2s_set_clock_rate() local
54 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val); in tegra210_i2s_set_clock_rate()
56 /* No need to set rates if I2S is being operated in slave */ in tegra210_i2s_set_clock_rate()
60 err = clk_set_rate(i2s->clk_i2s, clock_rate); in tegra210_i2s_set_clock_rate()
62 dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n", in tegra210_i2s_set_clock_rate()
67 if (!IS_ERR(i2s->clk_sync_input)) { in tegra210_i2s_set_clock_rate()
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H A Dtegra20_spdif.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * tegra20_spdif.c - Tegra20 SPDIF driver
6 * Copyright (C) 2011-2012 - NVIDIA, Inc.
32 regcache_cache_only(spdif->regmap, true); in tegra20_spdif_runtime_suspend()
34 clk_disable_unprepare(spdif->clk_spdif_out); in tegra20_spdif_runtime_suspend()
44 ret = reset_control_assert(spdif->reset); in tegra20_spdif_runtime_resume()
48 ret = clk_prepare_enable(spdif->clk_spdif_out); in tegra20_spdif_runtime_resume()
56 ret = reset_control_deassert(spdif->reset); in tegra20_spdif_runtime_resume()
60 regcache_cache_only(spdif->regmap, false); in tegra20_spdif_runtime_resume()
61 regcache_mark_dirty(spdif->regmap); in tegra20_spdif_runtime_resume()
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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dintel,keembay-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/sound/intel,keembay-i2s.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel KeemBay I2S
11 - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
12 - Paul J. Murphy <paul.j.murphy@intel.com>
15 Intel KeemBay I2S
18 - $ref: dai-common.yaml#
23 - intel,keembay-i2s
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/openbmc/linux/sound/soc/jz4740/
H A Djz4740-i2s.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/dma-mapping.h>
97 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); in jz4740_i2s_startup() local
105 if (!i2s->soc_info->shared_fifo_flush) { in jz4740_i2s_startup()
106 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in jz4740_i2s_startup()
107 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); in jz4740_i2s_startup()
109 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_RFLUSH); in jz4740_i2s_startup()
121 if (i2s->soc_info->shared_fifo_flush) in jz4740_i2s_startup()
122 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); in jz4740_i2s_startup()
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/openbmc/linux/sound/soc/fsl/
H A Dmpc5200_psc_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // Freescale MPC5200 PSC in I2S mode
22 * PSC_I2S_RATES: sample rates supported by the I2S
24 * This driver currently only supports the PSC running in I2S slave mode,
32 * PSC_I2S_FORMATS: audio formats supported by the PSC I2S mode
45 dev_dbg(psc_dma->dev, "%s(substream=%p) p_size=%i p_bytes=%i" in psc_i2s_hw_params()
65 dev_dbg(psc_dma->dev, "invalid format\n"); in psc_i2s_hw_params()
66 return -EINVAL; in psc_i2s_hw_params()
68 out_be32(&psc_dma->psc_regs->sicr, psc_dma->sicr | mode); in psc_i2s_hw_params()
91 dev_dbg(psc_dma->dev, "psc_i2s_set_sysclk(cpu_dai=%p, dir=%i)\n", in psc_i2s_set_sysclk()
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/openbmc/linux/sound/soc/samsung/
H A Didma.c1 // SPDX-License-Identifier: GPL-2.0+
3 // idma.c - I2S0 internal DMA driver
10 #include <linux/dma-mapping.h>
17 #include "i2s.h"
19 #include "i2s-regs.h"
52 void __iomem *regs; member
61 (readl(idma.regs + I2STRNCNT) & 0xffffff) * 4; in idma_getpos()
66 struct snd_pcm_runtime *runtime = substream->runtime; in idma_enqueue()
67 struct idma_ctrl *prtd = substream->runtime->private_data; in idma_enqueue()
70 spin_lock(&prtd->lock); in idma_enqueue()
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H A Dodroid.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
12 #include "i2s.h"
13 #include "i2s-regs.h"
28 struct snd_pcm_runtime *runtime = substream->runtime; in odroid_card_fe_startup()
39 struct odroid_priv *priv = snd_soc_card_get_drvdata(rtd->card); in odroid_card_fe_hw_params()
43 spin_lock_irqsave(&priv->lock, flags); in odroid_card_fe_hw_params()
44 if (priv->be_active && priv->be_sample_rate != params_rate(params)) in odroid_card_fe_hw_params()
45 ret = -EINVAL; in odroid_card_fe_hw_params()
46 spin_unlock_irqrestore(&priv->lock, flags); in odroid_card_fe_hw_params()
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/openbmc/linux/sound/soc/rockchip/
H A Drockchip_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
7 * Author: Jianqun <jay.xu@rock-chips.com>
25 #define DRV_NAME "rockchip-i2s"
49 * I2S controller hopes to start the tx and rx together,
63 static int i2s_pinctrl_select_bclk_on(struct rk_i2s_dev *i2s) in i2s_pinctrl_select_bclk_on() argument
67 if (!IS_ERR(i2s->pinctrl) && !IS_ERR_OR_NULL(i2s->bclk_on)) in i2s_pinctrl_select_bclk_on()
68 ret = pinctrl_select_state(i2s->pinctrl, i2s->bclk_on); in i2s_pinctrl_select_bclk_on()
71 dev_err(i2s->dev, "bclk enable failed %d\n", ret); in i2s_pinctrl_select_bclk_on()
76 static int i2s_pinctrl_select_bclk_off(struct rk_i2s_dev *i2s) in i2s_pinctrl_select_bclk_off() argument
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H A Drockchip_i2s_tdm.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver
5 // Author: Sugar Zhang <sugar.zhang@rock-chips.com>
9 #include <linux/clk-provider.h>
25 #define DRV_NAME "rockchip-i2s-tdm"
93 clk_disable_unprepare(i2s_tdm->mclk_tx); in i2s_tdm_disable_unprepare_mclk()
94 clk_disable_unprepare(i2s_tdm->mclk_rx); in i2s_tdm_disable_unprepare_mclk()
98 * i2s_tdm_prepare_enable_mclk - prepare to enable all mclks, disable them on
111 ret = clk_prepare_enable(i2s_tdm->mclk_tx); in i2s_tdm_prepare_enable_mclk()
114 ret = clk_prepare_enable(i2s_tdm->mclk_rx); in i2s_tdm_prepare_enable_mclk()
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/openbmc/linux/sound/soc/cirrus/
H A Dep93xx-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/sound/soc/ep93xx-i2s.c
4 * EP93xx I2S driver
27 #include <linux/platform_data/dma-ep93xx.h>
30 #include "ep93xx-pcm.h"
60 * 0 - Generate interrupt when FIFO is half empty
61 * 1 - Generate interrupt when FIFO is empty
78 void __iomem *regs; member
85 .name = "i2s-pcm-out",
90 .name = "i2s-pcm-in",
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/openbmc/linux/sound/soc/bcm/
H A Dbcm63xx-i2s-whistler.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 // linux/sound/bcm/bcm63xx-i2s-whistler.c
3 // BCM63xx whistler i2s driver
5 // Author: Kevin-Ke Li <kevin-ke.li@broadcom.com>
8 #include <linux/dma-mapping.h>
14 #include "bcm63xx-i2s.h"
16 #define DRV_NAME "brcm-i2s"
81 ret = clk_set_rate(i2s_priv->i2s_clk, params_rate(params)); in bcm63xx_i2s_hw_params()
83 dev_err(i2s_priv->dev, in bcm63xx_i2s_hw_params()
94 struct regmap *regmap_i2s = i2s_priv->regmap_i2s; in bcm63xx_i2s_startup()
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/openbmc/linux/sound/soc/sunxi/
H A Dsun4i-i2s.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
22 #include <sound/soc-dai.h>
85 #define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0)
93 /* Defines required for sun8i-h3 support */
106 #define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)
119 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) ((chan - 1) << 4)
121 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1)
128 #define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4)
133 /* Defines required for sun50i-h6 support */
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/openbmc/linux/arch/arm/mach-s3c/
H A Dpl080.c1 // SPDX-License-Identifier: GPL-2.0
3 // Samsung's S3C64XX generic DMA support using amba-pl08x driver.
17 #include "regs-sys-s3c64xx.h"
21 return cd->min_signal; in pl08x_get_xfer_signal()
117 { "s3c6400-uart.0", "tx", &s3c64xx_dma0_info[0] },
118 { "s3c6400-uart.0", "rx", &s3c64xx_dma0_info[1] },
119 { "s3c6400-uart.1", "tx", &s3c64xx_dma0_info[2] },
120 { "s3c6400-uart.1", "rx", &s3c64xx_dma0_info[3] },
121 { "s3c6400-uart.2", "tx", &s3c64xx_dma0_info[4] },
122 { "s3c6400-uart.2", "rx", &s3c64xx_dma0_info[5] },
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/openbmc/u-boot/drivers/clk/
H A Dclk_stm32h7.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
8 #include <clk-uclass.h>
15 #include <dt-bindings/clock/stm32h7-clks.h>
348 struct stm32_rcc_regs *regs = priv->rcc_base; in configure_clocks() local
349 uint8_t *pwr_base = (uint8_t *)regmap_get_range(priv->pwr_regmap, 0); in configure_clocks()
355 setbits_le32(&regs->cr, RCC_CR_HSION); in configure_clocks()
356 while (!(readl(&regs->cr) & RCC_CR_HSIRDY)) in configure_clocks()
360 writel(0, &regs->cfgr); in configure_clocks()
363 writel(0x0, &regs->d1ccipr); in configure_clocks()
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/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-388-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-88F6820)
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 /dts-v1/;
12 #include "armada-388.dtsi"
16 compatible = "marvell,a385-db", "marvell,armada388",
20 stdout-path = "serial0:115200n8";
35 internal-regs {
38 clock-frequency = <100000>;
39 audio_codec: audio-codec@4a {
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