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/openbmc/phosphor-power/tools/power-utils/
H A Daei_updater.cpp8 * http://www.apache.org/licenses/LICENSE-2.0
26 #include <phosphor-logging/lg2.hpp>
35 constexpr int ISP_STATUS_DELAY = 1200; // Delay for ISP status check (1.2s)
43 constexpr uint8_t BLOCK_WRITE_SIZE = 0x25; // I2C block write size
53 constexpr uint8_t ISP_MEMORY_REGISTER = 0xF9; // ISP memory register
55 // Define AEI ISP status register commands
57 constexpr uint8_t CMD_RESET_SEQ = 0x01; // This command will reset ISP OS for
60 constexpr uint8_t CMD_BOOT_ISP = 0x02; // Boot the In-System Programming System.
64 // Define AEI ISP response status bit
65 constexpr uint8_t B_ISP_MODE = 0x40; // ISP mod
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H A Daei_updater.hpp8 * http://www.apache.org/licenses/LICENSE-2.0
26 * This class provides methods to update firmware by writing ISP keys,
27 * validating firmware files, and performing I2C communications. It includes
62 * @brief Writes an ISP (In-System Programming) key to initiate the update.
69 * @brief Writes the mode required for ISP to start firmware programming.
76 * @brief Resets the ISP status to prepare for a firmware update.
137 * @brief Performs an I2C write and read with retry logic.
145 * @param expectedReadSize The size of data read from i2c device.
156 * @brief Performs a single I2C writ
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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dsamsung,exynos4212-fimc-is.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/media/samsung,exynos4212-fimc-is.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos4212/4412 SoC Imaging Subsystem (FIMC-IS)
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 The FIMC-IS is a subsystem for processing image signal from an image sensor.
15 The Exynos4x12 SoC series FIMC-IS V1.5 comprises of a dedicated ARM Cortex-A5
16 processor, ISP, DRC and FD IP blocks and peripheral devices such as UART, I2C
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H A Drockchip-isp1.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Helen Koike <helen.koike@collabora.com>
19 - rockchip,px30-cif-isp
20 - rockchip,rk3399-cif-isp
29 interrupt-names:
31 - const: isp
32 - const: mi
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H A Dsamsung,fimc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 The S5P/Exynos SoC Camera subsystem comprises of multiple sub-devices
17 CSIS, FIMC-LITE and FIMC-IS (ISP).
25 '#address-cells':
28 '#size-cells':
31 '#clock-cells':
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H A Dsamsung,s5c73m3.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5C73M3 8Mp camera ISP
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 The S5C73M3 camera ISP supports MIPI CSI-2 and parallel (ITU-R BT.656)
15 video data busses. The I2C bus is the main control bus and additionally the
31 clock-names:
33 - const: cis_extclk
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/openbmc/linux/drivers/usb/phy/
H A Dphy-isp1301.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/i2c.h>
31 MODULE_DEVICE_TABLE(i2c, isp1301_id);
41 static int __isp1301_write(struct isp1301 *isp, u8 reg, u8 value, u8 clear) in __isp1301_write() argument
43 return i2c_smbus_write_byte_data(isp->client, reg | clear, value); in __isp1301_write()
46 static int isp1301_write(struct isp1301 *isp, u8 reg, u8 value) in isp1301_write() argument
48 return __isp1301_write(isp, reg, value, 0); in isp1301_write()
51 static int isp1301_clear(struct isp1301 *isp, u8 reg, u8 value) in isp1301_clear() argument
53 return __isp1301_write(isp, reg, value, ISP1301_I2C_REG_CLEAR_ADDR); in isp1301_clear()
58 struct isp1301 *isp = phy_to_isp(phy); in isp1301_phy_init() local
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/openbmc/linux/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-is-i2c.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
12 #include <linux/i2c.h>
16 #include "fimc-is-i2c.h"
24 * An empty algorithm is used as the actual I2C bus controller driver
25 * is implemented in the FIMC-IS subsystem firmware and the host CPU
26 * doesn't access the I2C bus controller.
39 struct device_node *node = pdev->dev.of_node; in fimc_is_i2c_probe()
44 isp_i2c = devm_kzalloc(&pdev->dev, sizeof(*isp_i2c), GFP_KERNEL); in fimc_is_i2c_probe()
46 return -ENOMEM; in fimc_is_i2c_probe()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
22 depends on I2C
33 module will be called s5p-fimc.
36 tristate "S5P/EXYNOS MIPI-CSI2 receiver (MIPI-CSIS) driver"
41 This is a V4L2 driver for Samsung S5P and EXYNOS4 SoC MIPI-CSI2
42 receiver (MIPI-CSIS) devices.
45 module will be called s5p-csis.
48 tristate "EXYNOS FIMC-LITE camera interface driver"
49 depends on I2C
55 This is a V4L2 driver for Samsung EXYNOS4/5 SoC FIMC-LITE camera
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 s5p-fimc-objs := fimc-core.o fimc-reg.o fimc-m2m.o fimc-capture.o media-dev.o
3 exynos-fimc-lite-objs += fimc-lite-reg.o fimc-lite.o
4 s5p-csis-objs := mipi-csis.o
5 exynos4-is-common-objs := common.o
7 exynos-fimc-is-objs := fimc-is.o fimc-isp.o fimc-is-sensor.o fimc-is-regs.o
8 exynos-fimc-is-objs += fimc-is-param.o fimc-is-errno.o fimc-is-i2c.o
11 exynos-fimc-is-objs += fimc-isp-video.o
14 obj-$(CONFIG_VIDEO_S5P_MIPI_CSIS) += s5p-csis.o
15 obj-$(CONFIG_VIDEO_EXYNOS_FIMC_LITE) += exynos-fimc-lite.o
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H A Dfimc-is-i2c.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
9 #define FIMC_IS_I2C_COMPATIBLE "samsung,exynos4212-i2c-isp"
H A Dfimc-is.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
20 #include <linux/i2c.h>
30 #include <media/videobuf2-dma-contig.h>
32 #include "media-dev.h"
33 #include "fimc-is.h"
34 #include "fimc-is-command.h"
35 #include "fimc-is-errno.h"
36 #include "fimc-is-i2c.h"
37 #include "fimc-is-param.h"
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H A Dfimc-is-sensor.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
39 * struct fimc_is_sensor - fimc-is sensor data structure
41 * @i2c_bus: ISP I2C bus index (0...1)
/openbmc/linux/Documentation/devicetree/bindings/media/i2c/
H A Dimi,rdacm2x-gmsl.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/media/i2c/imi,rdacm2x-gmsl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jacopo Mondi <jacopo+renesas@jmondi.org>
12 - Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
13 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 - Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
16 description: -|
17 The IMI D&D RDACM20 and RDACM21 are GMSL-compatible camera designed for
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H A Dsamsung,s5k5baf.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/media/i2c/samsung,s5k5baf.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5K5BAF UXGA 1/5" 2M CMOS Image Sensor with embedded SoC ISP
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
22 clock-names:
24 - const: mclk
26 clock-frequency:
30 rstn-gpios:
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/openbmc/u-boot/doc/device-tree-bindings/gpu/
H A Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 - interrupts: The interrupt outputs from the controller.
7 - #address-cells: The number of cells used to represent physical base addresses
9 - #size-cells: The number of cells used to represent the size of an address
11 - ranges: The mapping of the host1x address space to the CPU address space.
12 - clocks: Must contain one entry, for the module clock.
13 See ../clocks/clock-bindings.txt for details.
14 - resets: Must contain an entry for each entry in reset-names.
16 - reset-names: Must include the following entries:
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/openbmc/linux/drivers/staging/media/atomisp/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 bool "Enable support to Intel Atom ISP camera drivers"
18 depends on I2C
30 bool "Use Intel Atom ISP on Cherrytail/Anniedale (ISP2401)"
33 Enable support for Atom ISP2401-based boards.
38 Disabling it enables support for Atom ISP2400-based boards
42 source "drivers/staging/media/atomisp/i2c/Kconfig"
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
5 obj-$(CONFIG_INTEL_ATOMISP) += i2c/
6 obj-$(CONFIG_VIDEO_ATOMISP) += atomisp.o
7 obj-$(CONFIG_VIDEO_ATOMISP) += pci/atomisp_gmin_platform.o
10 DEFINES += -DDEBUG
14 # SPDX-License-Identifier: GPL-2.0
15 atomisp-objs += \
52 pci/isp/kernels/aa/aa_2/ia_css_aa2.host.o \
53 pci/isp/kernels/anr/anr_1.0/ia_css_anr.host.o \
54 pci/isp/kernels/anr/anr_2/ia_css_anr2.host.o \
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/openbmc/linux/drivers/media/i2c/
H A Drdacm21.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2017-2020 Jacopo Mondi
6 * Copyright (C) 2017-2019 Kieran Bingham
7 * Copyright (C) 2017-2019 Laurent Pinchart
8 * Copyright (C) 2017-2019 Niklas Söderlund
16 #include <linux/i2c.h>
21 #include <media/v4l2-async.h>
22 #include <media/v4l2-ctrls.h>
23 #include <media/v4l2-subdev.h>
80 struct i2c_client *isp; member
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/openbmc/linux/drivers/media/platform/renesas/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
18 tristate "R-Car Image Signal Processor (ISP)"
27 Support for Renesas R-Car Image Signal Processor (ISP).
28 Enable this to support the Renesas R-Car Image Signal
29 Processor (ISP).
32 module will be called rcar-isp.
37 depends on VIDEO_DEV && I2C
43 source "drivers/media/platform/renesas/rcar-vin/Kconfig"
44 source "drivers/media/platform/renesas/rzg2l-cru/Kconfig"
56 Renesas R-Car Gen3 and RZ/G2 SoCs. It handles memory access for
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/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos4412-galaxy-s3.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/leds/common.h>
11 #include "exynos4412-midas.dtsi"
19 led-controller {
21 flen-gpios = <&gpj1 1 GPIO_ACTIVE_HIGH>;
22 enset-gpios = <&gpj1 2 GPIO_ACTIVE_HIGH>;
24 pinctrl-names = "default", "host", "isp";
25 pinctrl-0 = <&camera_flash_host>;
26 pinctrl-1 = <&camera_flash_host>;
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H A Dexynos4x12.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
27 fimc-lite0 = &fimc_lite_0;
28 fimc-lite1 = &fimc_lite_1;
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
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/openbmc/linux/Documentation/driver-api/media/
H A Dcamera-sensor.rst1 .. SPDX-License-Identifier: GPL-2.0
6 CSI-2 and parallel (BT.601 and BT.656) busses
7 ---------------------------------------------
9 Please see :ref:`transmitter-receiver`.
12 ---------------
23 elsewhere. Therefore only the pre-determined frequencies are configurable by the
29 Read the ``clock-frequency`` _DSD property to denote the frequency. The driver
35 The currently preferred way to achieve this is using ``assigned-clocks``,
36 ``assigned-clock-parents`` and ``assigned-clock-rates`` properties. See
37 ``Documentation/devicetree/bindings/clock/clock-bindings.txt`` for more
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/openbmc/linux/drivers/staging/media/omap4iss/
H A Diss.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <linux/dma-mapping.h>
14 #include <linux/i2c.h>
23 #include <media/v4l2-common.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-ctrls.h>
31 dev_dbg(iss->dev, "###ISS " #name "=0x%08x\n", \
36 dev_dbg(iss->dev, "-------------ISS HL Register dump-------------\n"); in iss_print_status()
47 dev_dbg(iss->dev, "-----------------------------------------------\n"); in iss_print_status()
51 * omap4iss_flush - Post pending L3 bus writes by doing a register readback
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/openbmc/u-boot/arch/arm/dts/
H A Dtegra210.dtsi1 #include <dt-bindings/clock/tegra210-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra210-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
10 interrupt-parent = <&lic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 pcie-controller@01003000 {
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