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/openbmc/qemu/target/ppc/
H A Dmmu_helper.c2 * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
25 #include "mmu-hash64.h"
26 #include "mmu-hash32.h"
27 #include "exec/exec-all.h"
28 #include "exec/page-protection.h"
31 #include "qemu/error-report.h"
32 #include "qemu/qemu-print.h"
34 #include "mmu-book3s-v3.h"
35 #include "mmu-radix64.h"
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H A Dmmu_common.c2 * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
25 #include "mmu-hash64.h"
26 #include "mmu-hash32.h"
27 #include "exec/exec-all.h"
28 #include "exec/page-protection.h"
31 #include "qemu/error-report.h"
32 #include "qemu/qemu-print.h"
34 #include "mmu-book3s-v3.h"
35 #include "mmu-radix64.h"
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/openbmc/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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H A Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
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/openbmc/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
20 i-cache-block-size = <64>;
21 i-cache-sets = <128>;
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/openbmc/qemu/accel/tcg/
H A Dcputlb.c2 * Common CPU TLB handling
21 #include "qemu/main-loop.h"
22 #include "hw/core/tcg-cpu-ops.h"
23 #include "exec/exec-all.h"
24 #include "exec/page-protection.h"
28 #include "exec/tb-flush.h"
29 #include "exec/memory-internal.h"
31 #include "exec/mmu-access-type.h"
32 #include "exec/tlb-common.h"
35 #include "qemu/error-report.h"
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/openbmc/qemu/target/sh4/
H A Dmonitor.c4 * Copyright (c) 2003-2004 Fabrice Bellard
27 #include "monitor/hmp-target.h"
30 static void print_tlb(Monitor *mon, int idx, tlb_t *tlb) in print_tlb() argument
32 monitor_printf(mon, " tlb%i:\t" in print_tlb()
33 "asid=%hhu vpn=%x\tppn=%x\tsz=%hhu size=%u\t" in print_tlb()
37 tlb->asid, tlb->vpn, tlb->ppn, tlb->sz, tlb->size, in print_tlb()
38 tlb->v, tlb->sh, tlb->c, tlb->pr, in print_tlb()
39 tlb->d, tlb->wt); in print_tlb()
45 int i; in hmp_info_tlb() local
53 for (i = 0 ; i < ITLB_SIZE ; i++) in hmp_info_tlb()
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/openbmc/linux/kernel/dma/
H A Dswiotlb.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * I/O TLBs (aka DMA address translation hardware).
9 * Copyright (C) 2000, 2003 Hewlett-Packard Co
10 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API.
14 * unnecessary i-cache flushing.
21 #define pr_fmt(fmt) "software IO TLB: " fmt
27 #include <linux/dma-direct.h>
28 #include <linux/dma-map-ops.h>
33 #include <linux/iommu-helper.h>
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/openbmc/linux/sound/pci/trident/
H A Dtrident_memory.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Trident 4DWave-NX memory page allocation (TLB area)
23 (trident)->tlb.entries[page] = cpu_to_le32((addr) & ~(SNDRV_TRIDENT_PAGE_SIZE-1))
25 (dma_addr_t)le32_to_cpu((trident->tlb.entries[page]) & ~(SNDRV_TRIDENT_PAGE_SIZE - 1))
28 /* page size == SNDRV_TRIDENT_PAGE_SIZE */
29 #define ALIGN_PAGE_SIZE PAGE_SIZE /* minimum page size for allocation */
31 /* fill TLB entrie(s) corresponding to page with ptr */
33 /* fill TLB entrie(s) corresponding to page with silence pointer */
34 #define set_silent_tlb(trident,page) __set_tlb_bus(trident, page, trident->tlb.silent_page->addr)
43 /* page size == SNDRV_TRIDENT_PAGE_SIZE x 2*/
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/openbmc/u-boot/doc/
H A DREADME.mpc85xx2 ----------------------
7 - MSR[DE] must be set
8 - A valid opcode must be fetchable, through the MMU, from the debug
11 To maximize the time during which this requirement is met, U-Boot sets MSR[DE]
12 immediately on entry and keeps it set. It also uses a temporary TLB to keep a
15 where U-Boot currently executes from.
21 ----------------
26 ----------------------------------------------
40 TLB Entries during u-boot execution
41 -----------------------------------
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/openbmc/linux/arch/powerpc/mm/
H A Dhugetlbpage.c2 * PPC Huge TLB Page Support for Kernel.
7 * Based on the IA-32 version:
23 #include <asm/tlb.h>
26 #include <asm/pte-walk.h>
33 #define PTE_T_ORDER (__builtin_ffs(sizeof(pte_basic_t)) - \
42 return __find_linux_pte(mm->pgd, addr, NULL, NULL); in huge_pte_offset()
51 int i; in __hugepte_alloc() local
56 num_hugepd = 1 << (pshift - pdshift); in __hugepte_alloc()
58 cachep = PGT_CACHE(pdshift - pshift); in __hugepte_alloc()
64 return -ENOMEM; in __hugepte_alloc()
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/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
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H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2011 Freescale Semiconductor, Inc.
20 void invalidate_tlb(u8 tlb) in invalidate_tlb() argument
22 if (tlb == 0) in invalidate_tlb()
24 if (tlb == 1) in invalidate_tlb()
30 int i; in init_tlbs() local
32 for (i = 0; i < num_tlb_entries; i++) { in init_tlbs()
33 write_tlb(tlb_table[i].mas0, in init_tlbs()
34 tlb_table[i].mas1, in init_tlbs()
35 tlb_table[i].mas2, in init_tlbs()
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/openbmc/linux/arch/sparc/mm/
H A Dhugetlbpage.c1 // SPDX-License-Identifier: GPL-2.0
3 * SPARC64 Huge TLB page support.
17 #include <asm/tlb.h>
22 /* Slightly simplified from the non-hugepage variant because by
48 VM_BUG_ON(addr != -ENOMEM); in hugetlb_get_unmapped_area_bottomup()
64 struct mm_struct *mm = current->mm; in hugetlb_get_unmapped_area_topdown()
68 /* This should only ever run for 32-bit processes. */ in hugetlb_get_unmapped_area_topdown()
74 info.high_limit = mm->mmap_base; in hugetlb_get_unmapped_area_topdown()
81 * so fall back to the bottom-up function here. This scenario in hugetlb_get_unmapped_area_topdown()
86 VM_BUG_ON(addr != -ENOMEM); in hugetlb_get_unmapped_area_topdown()
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/openbmc/qemu/target/loongarch/tcg/
H A Dtlb_helper.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * QEMU LoongArch TLB helpers
10 #include "qemu/guest-random.h"
14 #include "exec/helper-proto.h"
15 #include "exec/exec-all.h"
16 #include "exec/page-protection.h"
19 #include "cpu-csr.h"
26 *dir_base = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR1_BASE); in get_dir_base_width()
27 *dir_width = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR1_WIDTH); in get_dir_base_width()
30 *dir_base = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR2_BASE); in get_dir_base_width()
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/openbmc/linux/arch/powerpc/boot/dts/
H A Dmicrowatt.dts1 /dts-v1/;
4 #size-cells = <0x02>;
5 #address-cells = <0x02>;
6 model-name = "microwatt";
7 compatible = "microwatt-soc";
13 reserved-memory {
14 #size-cells = <0x02>;
15 #address-cells = <0x02>;
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
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/openbmc/linux/Documentation/devicetree/bindings/riscv/
H A Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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/openbmc/qemu/target/hppa/
H A Dmachine.c25 static int get_psw(QEMUFile *f, void *opaque, size_t size, in get_psw() argument
33 static int put_psw(QEMUFile *f, void *opaque, size_t size, in put_psw() argument
47 static int get_tlb(QEMUFile *f, void *opaque, size_t size, in get_tlb() argument
53 ent->itree.start = qemu_get_be64(f); in get_tlb()
54 ent->itree.last = qemu_get_be64(f); in get_tlb()
55 ent->pa = qemu_get_be64(f); in get_tlb()
59 ent->t = extract64(val, 61, 1); in get_tlb()
60 ent->d = extract64(val, 60, 1); in get_tlb()
61 ent->b = extract64(val, 59, 1); in get_tlb()
62 ent->ar_type = extract64(val, 56, 3); in get_tlb()
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/openbmc/linux/include/asm-generic/
H A Dtlb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* include/asm-generic/tlb.h
4 * Generic TLB shootdown code
32 * Generic MMU-gather implementation.
35 * correct and efficient ordering of freeing pages and TLB invalidations.
40 * 2) TLB invalidate page
49 * - tlb_gather_mmu() / tlb_gather_mmu_fullmm() / tlb_finish_mmu()
53 * Finish in particular will issue a (final) TLB invalidate and free
56 * - tlb_start_vma() / tlb_end_vma(); marks the start / end of a VMA
61 * - tlb_remove_table()
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/openbmc/linux/arch/powerpc/mm/book3s64/
H A Dhash_tlb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * TLB and MMU hash table.
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
25 #include <asm/tlb.h>
27 #include <asm/pte-walk.h>
49 int i, offset; in hpte_need_flush() local
51 i = batch->index; in hpte_need_flush()
54 * Get page size (maybe move back to caller). in hpte_need_flush()
57 * for SPEs, we obtain the page size from the slice, which thus in hpte_need_flush()
64 /* Mask the address for the correct page size */ in hpte_need_flush()
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/openbmc/qemu/target/sparc/
H A Dldst_helper.c4 * Copyright (c) 2003-2005 Fabrice Bellard
25 #include "exec/helper-proto.h"
26 #include "exec/exec-all.h"
27 #include "exec/page-protection.h"
65 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
72 /* Calculates TSB pointer value for fault page size
74 * UA2005 holds the page size configuration in mmu_ctx registers */
82 int ctx = mmu->tag_access & 0x1fffULL; in ultrasparc_tsb_pointer()
83 uint64_t ctx_register = mmu->sun4v_ctx_config[ctx ? 1 : 0]; in ultrasparc_tsb_pointer()
88 tsb_register = mmu->sun4v_tsb_pointers[tsb_index]; in ultrasparc_tsb_pointer()
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/openbmc/qemu/target/riscv/
H A Dpmp.c2 * QEMU RISC-V PMP (Physical Memory Protection)
7 * This provides a RISC-V Physical Memory Protection implementation
27 #include "exec/exec-all.h"
28 #include "exec/page-protection.h"
53 if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) { in pmp_is_locked()
70 return env->pmp_state.num_rules; in pmp_get_num_rules()
79 return env->pmp_state.pmp[pmp_index].cfg_reg; in pmp_read_cfg()
95 if (riscv_cpu_cfg(env)->ext_smepmp) { in pmp_write_cfg()
125 qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n"); in pmp_write_cfg()
126 } else if (env->pmp_state.pmp[pmp_index].cfg_reg != val) { in pmp_write_cfg()
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/openbmc/linux/Documentation/core-api/
H A Dcachetlb.rst2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
27 possible for stale translations to exist in this "TLB" cache.
44 the TLB. After running, this interface must make sure that
47 there will be no entries in the TLB for 'mm'.
57 address translations from the TLB. After running, this
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/openbmc/linux/arch/nios2/kernel/
H A Dcpuinfo.c1 // SPDX-License-Identifier: GPL-2.0-or-later
41 if (!of_property_read_bool(cpu, "altr,has-initda")) in setup_cpuinfo()
43 "hardware system to have more than 4-byte line data " in setup_cpuinfo()
46 cpuinfo.cpu_clock_freq = fcpu(cpu, "clock-frequency"); in setup_cpuinfo()
54 cpuinfo.has_div = of_property_read_bool(cpu, "altr,has-div"); in setup_cpuinfo()
55 cpuinfo.has_mul = of_property_read_bool(cpu, "altr,has-mul"); in setup_cpuinfo()
56 cpuinfo.has_mulx = of_property_read_bool(cpu, "altr,has-mulx"); in setup_cpuinfo()
57 cpuinfo.has_bmx = of_property_read_bool(cpu, "altr,has-bmx"); in setup_cpuinfo()
58 cpuinfo.has_cdx = of_property_read_bool(cpu, "altr,has-cdx"); in setup_cpuinfo()
59 cpuinfo.mmu = of_property_read_bool(cpu, "altr,has-mmu"); in setup_cpuinfo()
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