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/openbmc/linux/include/dt-bindings/pinctrl/
H A Dk210-fpioa.h1 /* SPDX-License-Identifier: GPL-2.0+ */
11 * kendryte-standalone-sdk/lib/drivers/include/fpioa.h
32 #define K210_PCF_UARTHS_RX 18 /* UART High speed Receiver */
33 #define K210_PCF_UARTHS_TX 19 /* UART High speed Transmitter */
38 #define K210_PCF_GPIOHS0 24 /* GPIO High speed 0 */
39 #define K210_PCF_GPIOHS1 25 /* GPIO High speed 1 */
40 #define K210_PCF_GPIOHS2 26 /* GPIO High speed 2 */
41 #define K210_PCF_GPIOHS3 27 /* GPIO High speed 3 */
42 #define K210_PCF_GPIOHS4 28 /* GPIO High speed 4 */
43 #define K210_PCF_GPIOHS5 29 /* GPIO High speed 5 */
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/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-pci-drivers-ehci_hcd7 PCI-based EHCI USB controllers (i.e., high-speed USB-2.0
9 "companion" full/low-speed USB-1.1 controllers. When a
10 high-speed device is plugged in, the connection is routed
11 to the EHCI controller; when a full- or low-speed device
15 Sometimes you want to force a high-speed device to connect
16 at full speed, which can be accomplished by forcing the
23 For example: To force the high-speed device attached to
24 port 4 on bus 2 to run at full speed::
28 To return the port to high-speed operation::
30 echo -4 >/sys/bus/usb/devices/usb2/../companion
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/openbmc/linux/Documentation/admin-guide/pm/
H A Dintel-speed-select.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Intel(R) Speed Select Technology User Guide
7 The Intel(R) Speed Select Technology (Intel(R) SST) provides a powerful new
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
21 and configure these features is by using the Intel Speed Select utility.
23 This document explains how to use the Intel Speed Select tool to enumerate and
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
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/openbmc/linux/Documentation/hwmon/
H A Dadm9240.rst10 Addresses scanned: I2C 0x2c - 0x2f
20 Addresses scanned: I2C 0x2c - 0x2f
24 http://pdfserv.maxim-ic.com/en/ds/DS1780.pdf
30 Addresses scanned: I2C 0x2c - 0x2f
37 - Frodo Looijaard <frodol@dds.nl>,
38 - Philip Edelbrock <phil@netroedge.com>,
39 - Michiel Rook <michiel@grendelproject.nl>,
40 - Grant Coady <gcoady.lk@gmail.com> with guidance
44 ---------
46 chip MSB 5-bit address. Each chip reports a unique manufacturer
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H A Dvt1211.rst10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
80 ------------------
82 Voltages are sampled by an 8-bit ADC with a LSB of ~10mV. The supported input
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/openbmc/linux/Documentation/usb/
H A Dehci.rst5 27-Dec-2002
7 The EHCI driver is used to talk to high speed USB 2.0 devices using
8 USB 2.0-capable host controller hardware. The USB 2.0 standard is
11 - "High Speed" 480 Mbit/sec (60 MByte/sec)
12 - "Full Speed" 12 Mbit/sec (1.5 MByte/sec)
13 - "Low Speed" 1.5 Mbit/sec
15 USB 1.1 only addressed full speed and low speed. High speed devices
23 (TT) in the hub, which turns low or full speed transactions into
24 high speed "split transactions" that don't waste transfer bandwidth.
31 While usb-storage devices have been available since mid-2001 (working
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/openbmc/linux/drivers/usb/gadget/udc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
7 # NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !!
9 # - Host systems (like PCs) need CONFIG_USB (with "A" jacks).
10 # - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks).
11 # - Some systems have both kinds of controllers.
13 # With help from a special transceiver and a "Mini-AB" jack, systems with
14 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
22 # - integrated/SOC controllers first
23 # - licensed IP used in both SOC and discrete versions
24 # - discrete ones (including all PCI-only controllers)
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/openbmc/linux/drivers/phy/qualcomm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
124 controllers on Qualcomm chips. This driver supports the high-speed
133 Enable support for the USB high-speed SNPS eUSB2 phy on Qualcomm
142 Enable support for the USB high-speed SNPS eUSB2 repeater on Qualcomm
160 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
163 Support for the USB high-speed ULPI compliant phy on Qualcomm
171 Enable support for the USB high-speed SNPS Femto phy on Qualcomm
184 tristate "Qualcomm 28nm High-Speed PHY"
186 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
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/openbmc/linux/drivers/usb/gadget/function/
H A Du_uvc.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Copyright (c) 2013-2014 Samsung Electronics Co., Ltd.
36 * Control descriptors array pointers for full-/high-speed and
37 * super-speed. They point by default to the uvc_fs_control_cls and
45 * Streaming descriptors array pointers for full-speed, high-speed and
46 * super-speed. They will point to the uvc_[fhs]s_streaming_cls arrays
47 * for configfs-based gadgets. Legacy gadgets must initialize them in
54 /* Default control descriptors for configfs-based gadgets. */
60 * Control descriptors pointers arrays for full-/high-speed and
61 * super-speed. The first element is a configurable control header
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/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu7_thermal.c32 if (hwmgr->thermal_controller.fanInfo.bNoFan) in smu7_fan_ctrl_get_fan_speed_info()
33 return -ENODEV; in smu7_fan_ctrl_get_fan_speed_info()
35 fan_speed_info->supports_percent_read = true; in smu7_fan_ctrl_get_fan_speed_info()
36 fan_speed_info->supports_percent_write = true; in smu7_fan_ctrl_get_fan_speed_info()
37 fan_speed_info->min_percent = 0; in smu7_fan_ctrl_get_fan_speed_info()
38 fan_speed_info->max_percent = 100; in smu7_fan_ctrl_get_fan_speed_info()
41 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) { in smu7_fan_ctrl_get_fan_speed_info()
42 fan_speed_info->supports_rpm_read = true; in smu7_fan_ctrl_get_fan_speed_info()
43 fan_speed_info->supports_rpm_write = true; in smu7_fan_ctrl_get_fan_speed_info()
44 fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM; in smu7_fan_ctrl_get_fan_speed_info()
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H A Dvega20_thermal.c34 struct vega20_hwmgr *data = hwmgr->backend; in vega20_disable_fan_control_feature()
37 if (data->smu_features[GNLD_FAN_CONTROL].supported) { in vega20_disable_fan_control_feature()
40 data->smu_features[GNLD_FAN_CONTROL]. in vega20_disable_fan_control_feature()
45 data->smu_features[GNLD_FAN_CONTROL].enabled = false; in vega20_disable_fan_control_feature()
53 struct vega20_hwmgr *data = hwmgr->backend; in vega20_fan_ctrl_stop_smc_fan_control()
55 if (data->smu_features[GNLD_FAN_CONTROL].supported) in vega20_fan_ctrl_stop_smc_fan_control()
63 struct vega20_hwmgr *data = hwmgr->backend; in vega20_enable_fan_control_feature()
66 if (data->smu_features[GNLD_FAN_CONTROL].supported) { in vega20_enable_fan_control_feature()
69 data->smu_features[GNLD_FAN_CONTROL]. in vega20_enable_fan_control_feature()
74 data->smu_features[GNLD_FAN_CONTROL].enabled = true; in vega20_enable_fan_control_feature()
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H A Dvega10_thermal.c42 if (hwmgr->thermal_controller.fanInfo.bNoFan) in vega10_fan_ctrl_get_fan_speed_info()
45 fan_speed_info->supports_percent_read = true; in vega10_fan_ctrl_get_fan_speed_info()
46 fan_speed_info->supports_percent_write = true; in vega10_fan_ctrl_get_fan_speed_info()
47 fan_speed_info->min_percent = 0; in vega10_fan_ctrl_get_fan_speed_info()
48 fan_speed_info->max_percent = 100; in vega10_fan_ctrl_get_fan_speed_info()
51 hwmgr->thermal_controller.fanInfo. in vega10_fan_ctrl_get_fan_speed_info()
53 fan_speed_info->supports_rpm_read = true; in vega10_fan_ctrl_get_fan_speed_info()
54 fan_speed_info->supports_rpm_write = true; in vega10_fan_ctrl_get_fan_speed_info()
55 fan_speed_info->min_rpm = in vega10_fan_ctrl_get_fan_speed_info()
56 hwmgr->thermal_controller.fanInfo.ulMinRPM; in vega10_fan_ctrl_get_fan_speed_info()
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/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
30 - Cryptography acceleration (SEC)
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/openbmc/smbios-mdr/tools/
H A Dsst-compare-redfish-os.py13 # * intel-speed-select tool from the kernel source tree
14 # (tools/power/x86/intel-speed-select), and available in the PATH.
29 # For TPMI-based CPUs, we only care about powerdomain-0
32 match = re.search("powerdomain-(\\d+)", proc)
41 "intel-speed-select",
42 "--debug",
43 "--format=json",
44 "perf-profile",
64 "intel-speed-select",
65 "--format=json",
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dusb.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
22 phy-names:
26 usb-phy:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
36 UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is selected, UTMI+ low
38 serial is specified and High-Speed Inter-Chip feature if HSIC is
44 maximum-speed:
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,usb-snps-femto-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-snps-femto-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Synopsys Femto High-Speed USB PHY V2
10 - Wesley Cheng <quic_wcheng@quicinc.com>
13 Qualcomm High-Speed USB PHY
18 - items:
19 - enum:
20 - qcom,sa8775p-usb-hs-phy
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/openbmc/linux/Documentation/devicetree/bindings/powerpc/4xx/
H A Dhsta.txt2 ppc476gtr High Speed Serial Assist (HSTA) node
5 The 476gtr SoC contains a high speed serial assist module attached
6 between the plb4 and plb6 system buses to provide high speed data
14 - compatible : "ibm,476gtr-hsta-msi", "ibm,hsta-msi"
15 - reg : register mapping for the HSTA MSI space
16 - interrupts : ordered interrupt mapping for each MSI in the register
/openbmc/u-boot/drivers/usb/gadget/
H A Depautoconf.c1 // SPDX-License-Identifier: GPL-2.0+
3 * epautoconf.c -- endpoint autoconfiguration for usb gadget drivers
7 * Ported to U-Boot by: Thomas Smits <ts.smits@gmail.com> and
34 * - ep1, ep2, ... address is fixed, not direction or type
35 * - ep1in, ep2out, ... address and direction are fixed, not type
36 * - ep1-bulk, ep2-bulk, ... address and type are fixed, not direction
37 * - ep1in-bulk, ep2out-iso, ... all three are fixed
38 * - ep-* ... no functionality restrictions
40 * Type suffixes are "-bulk", "-iso", or "-int". Numbers are decimal.
57 if (NULL != ep->driver_data) in ep_matches()
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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
42 cd-gpios:
47 non-removable:
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/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Dst,stm32-pinctrl.txt5 also provides ability to multiplex and configure the output of various on-chip
10 - compatible: value should be one of the following:
11 (a) "st,stm32f429-pinctrl"
12 (b) "st,stm32f746-pinctrl"
13 - #address-cells: The value of this property must be 1
14 - #size-cells : The value of this property must be 1
15 - ranges : defines mapping between pin controller node (parent) to
16 gpio-bank node (children).
17 - pins-are-numbered: Specify the subnodes are using numbered pinmux to
22 - gpio-controller : Indicates this device is a GPIO controller
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/openbmc/linux/arch/arm/boot/dts/st/
H A Dstih410-b2260.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
12 compatible = "st,stih410-b2260", "st,stih410";
15 stdout-path = &uart1;
29 compatible = "gpio-leds";
30 led-user-green-1 {
33 linux,default-trigger = "heartbeat";
34 default-state = "off";
37 led-user-green-2 {
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/openbmc/u-boot/arch/arm/dts/
H A Dstih410-b2260.dts9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
15 compatible = "st,stih410-b2260", "st,stih410";
19 linux,stdout-path = &uart1;
20 stdout-path = &uart1;
36 compatible = "gpio-leds";
40 linux,default-trigger = "heartbeat";
41 default-state = "off";
47 default-state = "off";
53 default-state = "off";
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_i2c_sw.c36 dce_i2c_sw->ctx = ctx; in dce_i2c_sw_construct()
46 dal_gpio_get_value(ddc->pin_data, &value); in read_bit_from_ddc()
48 dal_gpio_get_value(ddc->pin_clock, &value); in read_bit_from_ddc()
61 dal_gpio_set_value(ddc->pin_data, value); in write_bit_to_ddc()
63 dal_gpio_set_value(ddc->pin_clock, value); in write_bit_to_ddc()
70 dal_ddc_close(dce_i2c_sw->ddc); in release_engine_dce_sw()
71 dce_i2c_sw->ddc = NULL; in release_engine_dce_sw()
120 --shift; in write_byte_sw()
123 /* The display sends ACK by preventing the SDA from going high in write_byte_sw()
125 * If the SDA goes high after that bit, it's a NACK in write_byte_sw()
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/openbmc/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_cyclone5_chameleon96.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
14 compatible = "novtech,chameleon96", "altr,socfpga-cyclone5", "altr,socfpga";
18 stdout-path = "serial0:115200n8";
28 compatible = "regulator-fixed";
29 regulator-name = "3.3V";
30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
35 compatible = "gpio-leds";
40 linux,default-trigger = "heartbeat";
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/openbmc/u-boot/board/freescale/ls1012afrdm/
H A DREADME2 --------
3 QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development
6 high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.
9 --------------------
10 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
14 -----------------------
15 - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
16 - 2 SGMII 1G PHYs
17 - DDR Controller
18 - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
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