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/openbmc/qemu/hw/riscv/
H A Driscv_hart.c6 * Holds the state of a homogeneous array of RISC-V harts
31 DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
48 object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type); in riscv_hart_realize()
49 qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); in riscv_hart_realize()
50 s->harts[idx].env.mhartid = s->hartid_base + idx; in riscv_hart_realize()
51 qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); in riscv_hart_realize()
52 return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp); in riscv_hart_realize()
60 s->harts = g_new0(RISCVCPU, s->num_harts); in riscv_harts_realize()
H A Dboot.c37 bool riscv_is_32bit(RISCVHartArrayState *harts) in riscv_is_32bit() argument
39 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(&harts->harts[0]); in riscv_is_32bit()
70 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, in riscv_calc_kernel_start_addr() argument
72 if (riscv_is_32bit(harts)) { in riscv_calc_kernel_start_addr()
79 const char *riscv_default_firmware_name(RISCVHartArrayState *harts) in riscv_default_firmware_name() argument
81 if (riscv_is_32bit(harts)) { in riscv_default_firmware_name()
219 RISCVHartArrayState *harts, in riscv_load_kernel() argument
263 if (riscv_is_32bit(harts)) { in riscv_load_kernel()
347 RISCVHartArrayState *harts, in riscv_rom_copy_firmware_info() argument
356 if (riscv_is_32bit(harts)) { in riscv_rom_copy_firmware_info()
[all …]
H A Dsifive_u.c23 * two harts and up to five harts.
181 riscv_isa_write_fdt(&s->soc.u_cpus.harts[cpu - 1], fdt, nodename); in create_fdt()
183 riscv_isa_write_fdt(&s->soc.e_cpus.harts[0], fdt, nodename); in create_fdt()
757 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); in type_init()
790 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); in sifive_u_soc_realize()
H A Dmicrochip_pfsoc.c22 * two harts and up to five harts.
156 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); in microchip_pfsoc_soc_instance_init()
167 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); in microchip_pfsoc_soc_instance_init()
H A Dspike.c116 riscv_isa_write_fdt(&s->soc[socket].harts[cpu], fdt, cpu_name); in create_fdt()
244 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", in spike_board_init()
H A Dshakti_c.c172 object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1, in shakti_c_soc_instance_init()
/openbmc/qemu/include/hw/riscv/
H A Dboot.h30 bool riscv_is_32bit(RISCVHartArrayState *harts);
34 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
40 const char *riscv_default_firmware_name(RISCVHartArrayState *harts);
47 RISCVHartArrayState *harts,
54 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
60 RISCVHartArrayState *harts,
H A Driscv_hart.h6 * Holds the state of a heterogeneous array of RISC-V harts
41 RISCVCPU *harts; member
H A Dboot_opensbi.h49 * stage while other HARTs are still running in the previous booting
79 * stage while other HARTs are still running in the previous booting
H A Dnuma.h57 * Returns: number of harts for a valid socket and -1 for an invalid socket
/openbmc/linux/arch/riscv/kernel/
H A Dsbi.c124 * sbi_shutdown() - Remove all the harts from executing supervisor code.
368 * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
369 * @cpu_mask: A cpu mask containing all the target harts.
382 * remote harts for a virtual address range belonging to a specific ASID or not.
384 * @cpu_mask: A cpu mask containing all the target harts.
408 * harts for the specified guest physical address range.
409 * @cpu_mask: A cpu mask containing all the target harts.
426 * remote harts for a guest physical address range belonging to a specific VMID.
428 * @cpu_mask: A cpu mask containing all the target harts.
447 * harts for the current guest virtual address range.
[all …]
H A Dmachine_kexec.c128 * harts and possibly devices etc) for a kexec reboot.
194 * executed. We assume at this point that all other harts are
H A Dsys_riscv.c202 * extensions are supported on all harts, and only supports the in hwprobe_one_pair()
318 * all harts, then assume all CPUs are the same, and allow the vDSO to in init_hwprobe_vdso_data()
/openbmc/linux/arch/riscv/mm/
H A Dcacheflush.c32 * informs the remote harts they need to flush their local instruction caches.
35 * IPIs for harts that are not currently executing a MM context and instead
55 * Flush the I$ of other harts concurrently executing, and mark them as in flush_icache_mm()
117 pr_warn("%s mismatched between harts %lu and %lu\n", in cbo_get_block_size()
H A Dcontext.c212 * The mm_cpumask indicates which harts' TLBs contain the virtual in set_mm()
289 * shoot downs, so instead we send an IPI that informs the remote harts they
292 * machine, ie 'make -j') we avoid the IPIs for harts that are not currently
/openbmc/linux/Documentation/riscv/
H A Dboot.rst68 - ``RISCV_BOOT_SPINWAIT``: the firmware releases all harts in the kernel, one hart
69 wins a lottery and executes the early boot code while the other harts are
73 initialization phase and then will start all other harts using the SBI HSM
/openbmc/qemu/hw/intc/
H A Driscv_aclint.c268 DEFINE_PROP_UINT32("num-harts", RISCVAclintMTimerState, num_harts, 1),
367 qdev_prop_set_uint32(dev, "num-harts", num_harts); in riscv_aclint_mtimer_create()
467 DEFINE_PROP_UINT32("num-harts", RISCVAclintSwiState, num_harts, 1),
543 qdev_prop_set_uint32(dev, "num-harts", num_harts); in riscv_aclint_swi_create()
H A Dsifive_plic.c119 /* raise irq on harts where this irq is enabled */ in sifive_plic_update()
294 * "MS,MS" 2 harts, 0-1 with M and S mode
295 * "M,MS,MS,MS,MS" 5 harts, 0 with M mode, 1-5 with M and S mode
H A Driscv_aplic.c616 * (b) the domain's harts implement supervisor mode in riscv_aplic_read()
736 * (b) the domain's harts implement supervisor mode in riscv_aplic_write()
910 DEFINE_PROP_UINT32("num-harts", RISCVAPLICState, num_harts, 0),
1012 qdev_prop_set_uint32(dev, "num-harts", num_harts); in riscv_aplic_create()
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.txt23 a PLIC interrupt property will typically list the HLICs for all present HARTs
H A Dsifive,plic-1.0.0.yaml18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dsifive,clint.yaml17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
/openbmc/linux/arch/csky/abiv2/
H A Dcacheflush.c81 * Flush the I$ of other harts concurrently executing, and mark them as in flush_icache_mm_range()
/openbmc/linux/drivers/clocksource/
H A Dtimer-riscv.c62 * It is guaranteed that all the timers across all the harts are synchronized
/openbmc/linux/Documentation/devicetree/bindings/riscv/
H A Dcpus.yaml24 having four harts.

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