Home
last modified time | relevance | path

Searched +full:half +full:- +full:bus (Results 1 – 25 of 659) sorted by relevance

12345678910>>...27

/openbmc/u-boot/common/
H A Dmiiphyutil.c1 // SPDX-License-Identifier: GPL-2.0+
8 * This provides a bit-banged interface to the ethernet MII management
50 if (strcmp(dev->name, devname) == 0) in miiphy_get_dev_by_name()
69 struct mii_dev *bus; in mdio_alloc() local
71 bus = malloc(sizeof(*bus)); in mdio_alloc()
72 if (!bus) in mdio_alloc()
73 return bus; in mdio_alloc()
75 memset(bus, 0, sizeof(*bus)); in mdio_alloc()
78 INIT_LIST_HEAD(&bus->link); in mdio_alloc()
80 return bus; in mdio_alloc()
[all …]
/openbmc/linux/drivers/media/usb/stk1160/
H A Dstk1160-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * <elezegarcia--a.t--gmail.com>
10 * <rmthomas--a.t--sciolus.org>
19 /* Power-on Strapping Data */
39 * Bit 0 - Horizontal Decimation Control
42 * Bit 1 - Decimates Half or More Column
43 * 0 Decimates less than half from original column,
45 * 1 Decimates half or more from original column,
47 * Bit 2 - Vertical Decimation Control
50 * Bit 3 - Vertical Greater or Equal to Half
[all …]
/openbmc/linux/arch/mips/include/asm/dec/
H A Dioasic_ints.h31 #define IO_INR_SCC0A_RXDMA 29 /* SCC0A receive half page */
41 #define IO_INR_SCC1A_RXDMA 25 /* SCC1A receive half page */
49 #define IO_INR_AB_TXDMA 27 /* ACCESS.bus transmit page end */
50 #define IO_INR_AB_TXERR 26 /* ACCESS.bus xmit memory read error */
51 #define IO_INR_AB_RXDMA 25 /* ACCESS.bus receive half page */
52 #define IO_INR_AB_RXERR 24 /* ACCESS.bus receive overrun */
61 * The lower 16 bits are system-specific and thus defined in
62 * system-specific headers.
H A Dinterrupts.h3 * with the machine-specific interrupt routines.
28 #define DEC_IRQ_AB_RECV 1 /* ACCESS.bus receive */
29 #define DEC_IRQ_AB_XMIT 2 /* ACCESS.bus transmit */
34 #define DEC_IRQ_HALT 7 /* HALT button or from ACCESS.Bus */
37 #define DEC_IRQ_BUS 10 /* memory, I/O bus read/write errors */
59 #define DEC_IRQ_SCC0A_RXDMA 30 /* SCC0A receive half page */
62 #define DEC_IRQ_AB_RXERR 33 /* ACCESS.bus receive overrun */
63 #define DEC_IRQ_AB_RXDMA 34 /* ACCESS.bus receive half page */
64 #define DEC_IRQ_AB_TXERR 35 /* ACCESS.bus xmit memory read/ovrn */
65 #define DEC_IRQ_AB_TXDMA 36 /* ACCESS.bus transmit page end */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments GPMC Bus Child Nodes
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
15 represents any device connected to the GPMC bus. It may be a Flash chip,
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
[all …]
H A Dintel,ixp4xx-expansion-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral properties for Intel IXP4xx Expansion Bus
10 The IXP4xx expansion bus controller handles access to devices on the
11 memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
15 - Linus Walleij <linus.walleij@linaro.org>
18 intel,ixp4xx-eb-t1:
23 intel,ixp4xx-eb-t2:
[all …]
/openbmc/linux/drivers/net/ethernet/cavium/liquidio/
H A Docteon_device.c7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
68 /* Max Txqs: Half for each of the two ports :max_iq/2 */
74 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
97 /* Max Txqs: Half for each of the two ports :max_iq/2 */
103 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
176 /* Max Txqs: Half for each of the two ports :max_iq/2 */
182 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
205 /* Max Txqs: Half for each of the two ports :max_iq/2 */
211 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
[all …]
/openbmc/u-boot/include/configs/
H A Dsbc8641d.h1 /* SPDX-License-Identifier: GPL-2.0+ */
62 * L2CR setup -- make sure this is right for your board!
77 * Base addresses -- Note these are effective addresses where the
178 /* EPLD - User switches, board id, LEDs */
182 /* Local bus SDRAM 128MB */
184 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */
186 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */
190 #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */
194 #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
198 #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
[all …]
/openbmc/linux/drivers/net/phy/
H A Dphy-core.c1 // SPDX-License-Identifier: GPL-2.0+
10 * phy_speed_to_str - Return a string representing the PHY link speed
57 return "Unsupported (update phy-core.c)"; in phy_speed_to_str()
63 * phy_duplex_to_str - Return string describing the duplex
70 return "Half"; in phy_duplex_to_str()
75 return "Unsupported (update phy-core.c)"; in phy_duplex_to_str()
80 * phy_rate_matching_to_str - Return a string describing the rate matching
94 return "open-loop"; in phy_rate_matching_to_str()
96 return "Unsupported (update phy-core.c)"; in phy_rate_matching_to_str()
101 * phy_interface_num_ports - Return the number of links that can be carried by
[all …]
H A Dphy_device.c1 // SPDX-License-Identifier: GPL-2.0+
32 #include <linux/pse-pd/pse.h>
153 /* 10/100 half/full*/ in features_init()
166 /* 10 half, P2MP, TP */ in features_init()
171 /* 10/100 half/full + 1000 half/full */ in features_init()
182 /* 10/100 half/full + 1000 half/full + fibre*/ in features_init()
196 /* 10/100 half/full + 1000 half/full + TP/MII/FIBRE/AUI/BNC/Backplane*/ in features_init()
207 /* 10/100 half/full + 1000 half/full + 10G full*/ in features_init()
240 put_device(&phydev->mdio.dev); in phy_device_free()
254 fwnode_handle_put(dev->fwnode); in phy_device_release()
[all …]
/openbmc/linux/drivers/media/pci/cx23885/
H A Dcx23885-cards.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <media/drv-intf/cx25840.h>
19 #include "netup-eeprom.h"
20 #include "netup-init.h"
21 #include "altera-ci.h"
24 #include "cx23888-ir.h"
29 "NetUP Dual DVB-T/C CI card revision");
35 "\t\t\tHVR-1250 (reported safe)\n"
41 /* ------------------------------------------------------------------ */
64 .name = "Hauppauge WinTV-HVR1800lp",
[all …]
/openbmc/u-boot/board/armadeus/apf27/
H A Dapf27.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
40 /* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */
43 /* external bus frequency (have to be a ACFG_CLK_FREQ ratio) */
57 /* external bus frequency (have to be a CONFIG_HCLK_FREQ ratio) */
60 /* external serial bus frequency (have to be a CONFIG_SPLL_FREQ ratio) */
66 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
90 #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
91 #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
100 #define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater
[all …]
/openbmc/linux/Documentation/spi/
H A Dspidev.rst5 SPI devices have a limited userspace API, supporting basic half-duplex
19 * Prototyping in an environment that's not crash-prone; stray pointers
38 - struct spi_device_id spidev_spi_ids[]: list of devices that can be
42 - struct of_device_id spidev_dt_ids[]: list of devices that can be
46 - struct acpi_device_id spidev_acpi_ids[]: list of devices that can
52 post a patch for spidev to the linux-spi@vger.kernel.org mailing list.
66 echo spidev > /sys/bus/spi/devices/spiB.C/driver_override
67 echo spiB.C > /sys/bus/spi/drivers/spidev/bind
74 For a SPI device with chipselect C on bus B, you should see:
101 Since this is a standard Linux device driver -- even though it just happens
[all …]
H A Dspi-summary.rst5 02-Feb-2012
8 ------------
17 clocking modes through which data is exchanged; mode-0 and mode-3 are most
32 - SPI may be used for request/response style device protocols, as with
35 - It may also be used to stream data in either direction (half duplex),
38 - Some devices may use eight bit words. Others may use different word
39 lengths, such as streams of 12-bit or 20-bit digital samples.
41 - Words are usually sent with their most significant bit (MSB) first,
44 - Sometimes SPI is used to daisy-chain devices, like shift registers.
51 SPI is only one of the names used by such four-wire protocols, and
[all …]
/openbmc/linux/Documentation/devicetree/bindings/i3c/
H A Di3c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: I3C bus
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
11 - Miquel Raynal <miquel.raynal@bootlin.com>
15 and a set of child nodes for each I2C or I3C slave on the bus. Each of them
16 may, during the life of the bus, request mastership.
20 pattern: "^i3c-master@[0-9a-f]+$"
22 "#address-cells":
[all …]
/openbmc/qemu/hw/sh4/
H A Dsh7750_regs.h2 * SH-7750 memory-mapped registers
6 * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.
8 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
55 /* Page Table Entry High register - PTEH */
64 /* Page Table Entry Low register - PTEL */
70 #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */
73 #define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */
74 #define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Drs485.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 direction for the built-in half-duplex mode. The properties described
11 hereafter shall be given to a half-duplex capable UART node.
14 - Rob Herring <robh@kernel.org>
17 rs485-rts-delay:
18 description: prop-encoded-array <a b>
19 $ref: /schemas/types.yaml#/definitions/uint32-array
21 - description: Delay between rts signal and beginning of data sent in
[all …]
/openbmc/linux/Documentation/networking/device_drivers/ethernet/3com/
H A D3c509.rst1 .. SPDX-License-Identifier: GPL-2.0
21 ethercards in Linux. These cards are commonly known by the most widely-used
22 card's 3Com model number, 3c509. They are all 10mb/s ISA-bus cards and shouldn't
23 be (but sometimes are) confused with the similarly-numbered PCI-bus "3c905"
28 - 3c509 (original ISA card)
29 - 3c509B (later revision of the ISA card; supports full-duplex)
30 - 3c589 (PCMCIA)
31 - 3c589B (later revision of the 3c589; supports full-duplex)
32 - 3c579 (EISA)
45 The driver allows boot- or load-time overriding of the card's detected IOADDR,
[all …]
/openbmc/u-boot/drivers/spi/
H A Dmt7621_spi.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Derived from the Linux driver version drivers/spi/spi-mt7621.c
7 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
8 * Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
50 setbits_le32(rs->base + MT7621_SPI_MASTER, in mt7621_spi_reset()
58 debug("%s: cs#%d -> %s\n", __func__, cs, enable ? "enable" : "disable"); in mt7621_spi_set_cs()
61 iowrite32(val, rs->base + MT7621_SPI_POLAR); in mt7621_spi_set_cs()
64 static int mt7621_spi_set_mode(struct udevice *bus, uint mode) in mt7621_spi_set_mode() argument
66 struct mt7621_spi *rs = dev_get_priv(bus); in mt7621_spi_set_mode()
70 reg = ioread32(rs->base + MT7621_SPI_MASTER); in mt7621_spi_set_mode()
[all …]
/openbmc/u-boot/include/usb/
H A Dfusbh200.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Dante Su <dantesu@faraday-tech.com>
15 } hccr; /* 0x00 - 0x0f: hccr */
18 } hcor; /* 0x10 - 0x33: hcor */
21 uint32_t bmcsr; /* 0x40: Bus Monitor Control Status Register */
22 uint32_t bmisr; /* 0x44: Bus Monitor Interrupt Status Register */
23 uint32_t bmier; /* 0x48: Bus Monitor Interrupt Enable Register */
33 /* Bus Monitor Control Status Register */
43 #define BMCSR_IRQLH (1 << 3) /* IRQ triggered at level-high */
44 #define BMCSR_IRQLL (0 << 3) /* IRQ triggered at level-low */
[all …]
/openbmc/qemu/include/hw/pci-host/
H A Dastro.h2 * HP-PARISC Astro Bus connector with Elroy PCI host bridges
12 #define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */
14 #define TYPE_ASTRO_CHIP "astro-chip"
17 #define TYPE_ELROY_PCI_HOST_BRIDGE "elroy-pcihost"
30 #define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */
43 /* PCI bus number (Elroy number) */
51 uint64_t mmio_base[(0x0250 - 0x200) / 8];
72 uint64_t ioc_ranges[(0x03d8 - 0x300) / 8];
/openbmc/u-boot/doc/device-tree-bindings/spi/
H A Dspi-bus.txt4 and a set of child nodes for each SPI slave on the bus. For this
10 - #address-cells - number of cells required to define a chip select
11 address on the SPI bus.
12 - #size-cells - should be zero.
13 - compatible - name of SPI bus controller following generic names
15 - cs-gpios - (optional) gpios chip select.
16 No other properties are required in the SPI bus node. It is assumed
17 that a driver for an SPI bus device will understand that it is an SPI bus.
20 flexible and non-standardized, it is left out of this binding with the
26 - num-cs : total number of chipselects
[all …]
/openbmc/linux/drivers/media/platform/renesas/rcar-vin/
H A Drcar-vin.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Driver for Renesas R-Car VIN
6 * Copyright (C) 2011-2013 Renesas Solutions Corp.
10 * Based on the soc-camera rcar_vin driver
18 #include <media/v4l2-async.h>
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-dev.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/videobuf2-v4l2.h>
[all …]
/openbmc/linux/arch/alpha/include/asm/
H A Dcore_irongate.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * IRONGATE is the internal name for the AMD-751 K7 core logic chipset
10 * which provides memory controller and PCI access for NAUTILUS-based
21 * The 21264 supports, and internally recognizes, a 44-bit physical
24 * half of the physical address space (PA[43]=0) and I/O address space
25 * resides in the upper half of the physical address space (PA[43]=1).
30 * through the routines given is 32-bit.
38 igcsr32 dev_vendor; /* 0x00 - device ID, vendor ID */
39 igcsr32 stat_cmd; /* 0x04 - status, command */
40 igcsr32 class; /* 0x08 - class code, rev ID */
[all …]
/openbmc/u-boot/arch/microblaze/cpu/
H A Dexception.c1 // SPDX-License-Identifier: GPL-2.0+
28 puts("Illegal op-code exception\n"); in _hw_exception_handler()
31 puts("Instruction bus error exception\n"); in _hw_exception_handler()
34 puts("Data bus error exception\n"); in _hw_exception_handler()
51 printf("Unaligned %sword access\n", ((state & 0x800) ? "" : "half")); in _hw_exception_handler()

12345678910>>...27