1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2e82a316dSKuo-Jung Su /* 3e82a316dSKuo-Jung Su * Faraday USB 2.0 EHCI Controller 4e82a316dSKuo-Jung Su * 5e82a316dSKuo-Jung Su * (C) Copyright 2010 Faraday Technology 6e82a316dSKuo-Jung Su * Dante Su <dantesu@faraday-tech.com> 7e82a316dSKuo-Jung Su */ 8e82a316dSKuo-Jung Su 9e82a316dSKuo-Jung Su #ifndef _FUSBH200_H 10e82a316dSKuo-Jung Su #define _FUSBH200_H 11e82a316dSKuo-Jung Su 12e82a316dSKuo-Jung Su struct fusbh200_regs { 13e82a316dSKuo-Jung Su struct { 14e82a316dSKuo-Jung Su uint32_t data[4]; 15e82a316dSKuo-Jung Su } hccr; /* 0x00 - 0x0f: hccr */ 16e82a316dSKuo-Jung Su struct { 17e82a316dSKuo-Jung Su uint32_t data[9]; 18e82a316dSKuo-Jung Su } hcor; /* 0x10 - 0x33: hcor */ 19e82a316dSKuo-Jung Su uint32_t easstr;/* 0x34: EOF&Async. Sched. Sleep Timer Register */ 20e82a316dSKuo-Jung Su uint32_t rsvd[2]; 21e82a316dSKuo-Jung Su uint32_t bmcsr; /* 0x40: Bus Monitor Control Status Register */ 22e82a316dSKuo-Jung Su uint32_t bmisr; /* 0x44: Bus Monitor Interrupt Status Register */ 23e82a316dSKuo-Jung Su uint32_t bmier; /* 0x48: Bus Monitor Interrupt Enable Register */ 24e82a316dSKuo-Jung Su }; 25e82a316dSKuo-Jung Su 26e82a316dSKuo-Jung Su /* EOF & Async. Schedule Sleep Timer Register */ 27e82a316dSKuo-Jung Su #define EASSTR_RUNNING (1 << 6) /* Put transceiver in running/resume mode */ 28e82a316dSKuo-Jung Su #define EASSTR_SUSPEND (0 << 6) /* Put transceiver in suspend mode */ 29e82a316dSKuo-Jung Su #define EASSTR_EOF2(x) (((x) & 0x3) << 4) /* EOF 2 Timing */ 30e82a316dSKuo-Jung Su #define EASSTR_EOF1(x) (((x) & 0x3) << 2) /* EOF 1 Timing */ 31e82a316dSKuo-Jung Su #define EASSTR_ASST(x) (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */ 32e82a316dSKuo-Jung Su 33e82a316dSKuo-Jung Su /* Bus Monitor Control Status Register */ 34e82a316dSKuo-Jung Su #define BMCSR_SPD_HIGH (2 << 9) /* Speed of the attached device */ 35e82a316dSKuo-Jung Su #define BMCSR_SPD_LOW (1 << 9) 36e82a316dSKuo-Jung Su #define BMCSR_SPD_FULL (0 << 9) 37e82a316dSKuo-Jung Su #define BMCSR_SPD_MASK (3 << 9) 38e82a316dSKuo-Jung Su #define BMCSR_SPD_SHIFT 9 39e82a316dSKuo-Jung Su #define BMCSR_SPD(x) ((x >> 9) & 0x03) 40e82a316dSKuo-Jung Su #define BMCSR_VBUS (1 << 8) /* VBUS Valid */ 41e82a316dSKuo-Jung Su #define BMCSR_VBUS_OFF (1 << 4) /* VBUS Off */ 42e82a316dSKuo-Jung Su #define BMCSR_VBUS_ON (0 << 4) /* VBUS On */ 43e82a316dSKuo-Jung Su #define BMCSR_IRQLH (1 << 3) /* IRQ triggered at level-high */ 44e82a316dSKuo-Jung Su #define BMCSR_IRQLL (0 << 3) /* IRQ triggered at level-low */ 45e82a316dSKuo-Jung Su #define BMCSR_HALFSPD (1 << 2) /* Half speed mode for FPGA test */ 46e82a316dSKuo-Jung Su #define BMCSR_HFT_LONG (1 << 1) /* HDISCON noise filter = 270 us*/ 47e82a316dSKuo-Jung Su #define BMCSR_HFT (0 << 1) /* HDISCON noise filter = 135 us*/ 48e82a316dSKuo-Jung Su #define BMCSR_VFT_LONG (1 << 1) /* VBUS noise filter = 472 us*/ 49e82a316dSKuo-Jung Su #define BMCSR_VFT (0 << 1) /* VBUS noise filter = 135 us*/ 50e82a316dSKuo-Jung Su 51e82a316dSKuo-Jung Su /* Bus Monitor Interrupt Status Register */ 52e82a316dSKuo-Jung Su /* Bus Monitor Interrupt Enable Register */ 53e82a316dSKuo-Jung Su #define BMISR_DMAERR (1 << 4) /* DMA error */ 54e82a316dSKuo-Jung Su #define BMISR_DMA (1 << 3) /* DMA complete */ 55e82a316dSKuo-Jung Su #define BMISR_DEVRM (1 << 2) /* device removed */ 56e82a316dSKuo-Jung Su #define BMISR_OVD (1 << 1) /* over-current detected */ 57e82a316dSKuo-Jung Su #define BMISR_VBUSERR (1 << 0) /* VBUS error */ 58e82a316dSKuo-Jung Su 59e82a316dSKuo-Jung Su #endif 60