| /openbmc/u-boot/arch/arm/dts/ |
| H A D | hi3798cv200.dtsi | 4 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
7 * SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/clock/histb-clock.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/reset/ti-syscon.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
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| H A D | armada-xp-mv78260.dtsi | 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
50 #include "armada-xp.dtsi"
54 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
63 #address-cells = <1>;
64 #size-cells = <0>;
65 enable-method = "marvell,armada-xp-smp";
69 compatible = "marvell,sheeva-v7";
72 clock-latency = <1000000>;
77 compatible = "marvell,sheeva-v7";
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| H A D | armada-xp-mv78460.dtsi | 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
50 #include "armada-xp.dtsi"
54 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
64 #address-cells = <1>;
65 #size-cells = <0>;
66 enable-method = "marvell,armada-xp-smp";
70 compatible = "marvell,sheeva-v7";
73 clock-latency = <1000000>;
78 compatible = "marvell,sheeva-v7";
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| H A D | armada-xp-mv78230.dtsi | 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
50 #include "armada-xp.dtsi"
54 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
62 #address-cells = <1>;
63 #size-cells = <0>;
64 enable-method = "marvell,armada-xp-smp";
68 compatible = "marvell,sheeva-v7";
71 clock-latency = <1000000>;
76 compatible = "marvell,sheeva-v7";
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| H A D | sama5d2.dtsi | 16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <0>;
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <0>;
29 compatible = "simple-bus";
30 #address-cells = <1>;
31 #size-cells = <1>;
32 u-boot,dm-pre-reloc;
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| H A D | sama5d3.dtsi | 2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
12 #include <dt-bindings/dma/at91.h>
13 #include <dt-bindings/pinctrl/at91.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/clock/at91.h>
21 interrupt-parent = <&aic>;
44 #address-cells = <1>;
45 #size-cells = <0>;
48 compatible = "arm,cortex-a5";
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| H A D | at91sam9261.dtsi | 2 * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC
4 * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
10 #include <dt-bindings/pinctrl/at91.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clock/at91.h>
18 interrupt-parent = <&aic>;
38 compatible = "arm,arm926ej-s";
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
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| H A D | armada-cp110-slave.dtsi | 4 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/comphy/comphy_data.h>
50 cp110-slave {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 interrupt-parent = <&gic>;
57 config-space {
58 #address-cells = <1>;
59 #size-cells = <1>;
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| H A D | da850.dtsi | 10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <1>;
27 intc: interrupt-controller@fffee000 {
28 compatible = "ti,cp-intc";
29 interrupt-controller;
30 #interrupt-cells = <1>;
31 ti,intc-size = <101>;
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| H A D | armada-cp110-master.dtsi | 4 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/comphy/comphy_data.h>
50 cp110-master {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 interrupt-parent = <&gic>;
57 config-space {
58 #address-cells = <1>;
59 #size-cells = <1>;
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| H A D | at91sam9n12.dtsi | 2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
11 #include <dt-bindings/dma/at91.h>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h>
20 interrupt-parent = <&aic>;
42 compatible = "arm,arm926ej-s";
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
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| /openbmc/u-boot/doc/device-tree-bindings/gpio/ |
| H A D | gpio.txt | 1 Specifying GPIO information for devices
5 -----------------
8 properties, each containing a 'gpio-list':
10 gpio-list ::= <single-gpio> [gpio-list]
11 single-gpio ::= <gpio-phandle> <gpio-specifier>
12 gpio-phandle : phandle to gpio controller node
13 gpio-specifier : Array of #gpio-cells specifying specific gpio
16 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
17 of this GPIO for the device. While a non-existent <name> is considered valid
21 GPIO properties can contain one or more GPIO phandles, but only in exceptional
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| H A D | snps,creg-gpio.txt | 1 GPIO via CREG (control registers) driver
5 [ not used | gpio-1 | gpio-0 | <-shift-> ] < 32 bit register
12 - compatible : "snps,creg-gpio"
13 - reg : Exactly one register range with length 0x4.
14 - #gpio-cells : Should be one - the pin number.
15 - gpio-controller : Marks the device node as a GPIO controller.
16 - gpio-count: Number of GPIO pins.
17 - gpio-bit-per-line: Number of bits per gpio line (see picture).
18 - gpio-first-shift: Shift (in bits) of the first GPIO field in register
20 - gpio-activate-val: Value should be set in corresponding field to set
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| H A D | mscc_sgpio.txt | 1 Microsemi Corporation (MSCC) Serial GPIO driver
3 The MSCC serial GPIO extends the number or GPIO's on the system by
6 effective GPIO count can be extended by up to 128 GPIO's per
10 - compatible : "mscc,luton-sgpio" or "mscc,ocelot-sgpio"
11 - clock: Reference clock used to generate clock divider setting. See
12 mscc,sgpio-frequency property.
13 - reg : Physical base address and length of the controller's registers.
14 - #gpio-cells : Should be two. The first cell is the pin number and the
16 - bit 0 specifies polarity (0 for normal, 1 for inverted)
17 - gpio-controller : Marks the device node as a GPIO controller.
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| H A D | bcm2835-gpio.txt | 1 * Broadcom BCM283x GPIO controller
4 - compatible: must be "brcm,bcm2835-gpio"
5 - reg: exactly one register range with length 0xb4
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| /openbmc/u-boot/drivers/gpio/ |
| H A D | sh_pfc.c | 2 * Pinmuxed GPIO support for SuperH.
23 if (enum_id < r->begin) in enum_in_range()
26 if (enum_id > r->end) in enum_in_range()
74 pos = dr->reg_width - (in_pos + 1); in gpio_read_bit()
77 dr->reg + offset, pos, dr->reg_width); in gpio_read_bit()
79 return (gpio_read_raw_reg(dr->mapped_reg + offset, in gpio_read_bit()
80 dr->reg_width) >> pos) & 1; in gpio_read_bit()
88 pos = dr->reg_width - (in_pos + 1); in gpio_write_bit()
92 dr->reg, !!value, pos, dr->reg_width); in gpio_write_bit()
95 __set_bit(pos, &dr->reg_shadow); in gpio_write_bit()
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| /openbmc/u-boot/drivers/led/ |
| H A D | Kconfig | 8 U-Boot provides a uclass API to implement this feature. LED drivers
9 can provide access to board-specific LEDs. Use of the device tree
50 bool "LED support for GPIO-connected LEDs"
53 Enable support for LEDs which are connected to GPIO lines. These
55 The GPIO driver must used driver model. LEDs are configured using
59 bool "LED support for GPIO-connected LEDs in SPL"
62 This option is an SPL-variant of the LED_GPIO option.
68 Allows common u-boot commands to use a board's leds to
90 bool "GPIO status LED implementation"
92 The status LED can be connected to a GPIO pin. In such cases, the
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| /openbmc/qemu/include/hw/misc/ |
| H A D | led.h | 4 * Copyright (C) 2020 Philippe Mathieu-Daudé <f4bug@amsat.org>
6 * SPDX-License-Identifier: GPL-2.0-or-later
12 #include "hw/qdev-core.h"
23 * https://www.lumileds.com/products/color-leds/luxeon-rebel-color/
25 typedef enum { /* Coarse wavelength range */
48 * Determines whether a GPIO is using a positive (active-high)
49 * logic (when used with GPIO, the intensity at reset is related
50 * to the GPIO polarity).
60 * @intensity_percent: intensity as percentage in range 0 to 100.
68 * Returns: The LED intensity as percentage in range 0 to 100.
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| H A D | tz-ppc.h | 13 * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM
15 * https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g
22 * The PPC has no register interface -- it is configured purely by a
24 * they are either hardwired or exposed in an ad-hoc register interface by
43 * range then no sysbus MMIO region is created for its upstream. When an
44 * unused port lies in the middle of the range with other used ports at
50 * + Named GPIO inputs "cfg_nonsec[0..15]": set to 1 if the port should be
52 * + Named GPIO inputs "cfg_ap[0..15]": set to 1 if the port should be
53 * accessible to non-privileged transactions
54 * + Named GPIO input "cfg_sec_resp": set to 1 if a rejected transaction should
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| /openbmc/u-boot/doc/device-tree-bindings/pinctrl/ |
| H A D | st,stm32-pinctrl.txt | 1 * STM32 GPIO and Pin Mux/Config controller
3 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
5 also provides ability to multiplex and configure the output of various on-chip
10 - compatible: value should be one of the following:
11 (a) "st,stm32f429-pinctrl"
12 (b) "st,stm32f746-pinctrl"
13 - #address-cells: The value of this property must be 1
14 - #size-cells : The value of this property must be 1
15 - ranges : defines mapping between pin controller node (parent) to
16 gpio-bank node (children).
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| H A D | marvell,armada-37xx-pinctrl.txt | 1 * Marvell Armada 37xx SoC pin and GPIO controller
3 Each Armada 37xx SoC comes with two pin and GPIO controllers, one for the
6 GPIO and pin controller:
7 ------------------------
11 Refer to pinctrl-bindings.txt in this directory for details of the
17 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
19 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
21 - reg: The first set of registers is for pinctrl/GPIO and the second
23 - interrupts: list of interrupts used by the GPIO
28 - pins 20-24
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| /openbmc/u-boot/board/gateworks/gw_ventana/ |
| H A D | gw_ventana.c | 1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/mx6-pins.h>
15 #include <asm/gpio.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/sata.h>
18 #include <asm/mach-imx/spi.h>
19 #include <asm/mach-imx/video.h>
107 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_gpmi_nand()
116 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
124 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
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| /openbmc/qemu/docs/system/arm/ |
| H A D | nrf.rst | 4 The `Nordic nRF`_ chips are a family of ARM-based System-on-Chip that
5 are designed to be used for low-power and short-range wireless solutions.
9 The nRF51 series is the first series for short range wireless applications.
13 - ``microbit`` BBC micro:bit board with nRF51822 SoC
19 -----------------
21 * ARM Cortex-M0 (ARMv6-M)
26 * GPIO controller
31 ---------------
34 * Real-Time Clock (RTC) controller
42 ------------
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| /openbmc/u-boot/doc/device-tree-bindings/pci/ |
| H A D | armada8k-pcie.txt | 1 Armada-8K PCIe DT details:
4 Armada-8k uses synopsis designware PCIe controller.
7 - compatible : should be "marvell,armada8k-pcie", "snps,dw-pcie".
8 - reg: base addresses and lengths of the pcie control and global control registers.
10 points to the pcie configuration registers as mentioned in dw-pcie dt bindings in the link below.
11 - interrupt-map-mask and interrupt-map, standard PCI properties to
13 - All other definitions as per generic PCI bindings
15 "Documentation/devicetree/bindings/pci/designware-pcie.txt"
18 PHY support is still not supported for armada-8k, once it will, the following parameters can be use…
19 - phys : phandle to phy node associated with pcie controller.
[all …]
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| /openbmc/qemu/include/hw/arm/ |
| H A D | bcm2838_peripherals.h | 6 * SPDX-License-Identifier: GPL-2.0-or-later
14 #include "hw/gpio/bcm2838_gpio.h"
53 #define TYPE_BCM2838_PERIPHERALS "bcm2838-peripherals"
67 BCM2838GpioState gpio; member
81 uint64_t peri_low_size; /* Peripheral lower range size */
|