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/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-latch.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-latch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO latch controller
10 - Sascha Hauer <s.hauer@pengutronix.de>
13 This binding describes a GPIO multiplexer based on latches connected to
16 CLK0 ----------------------. ,--------.
17 CLK1 -------------------. `--------|> #0 |
19 OUT0 ----------------+--|-----------|D0 Q0|-----|<
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H A Dsprd,gpio-eic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/gpio/sprd,gpio-eic.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
19 controller contains 4 sub-modules, i.e. EIC-debounce, EIC-latch, EIC-async and
20 EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub-
23 The EIC-debounce sub-module provides up to 8 source input signal
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/openbmc/linux/drivers/gpio/
H A Dgpio-latch.c1 // SPDX-License-Identifier: GPL-2.0
3 * GPIO latch driver
7 * This driver implements a GPIO (or better GPO as there is no input)
10 * CLK0 ----------------------. ,--------.
11 * CLK1 -------------------. `--------|> #0 |
13 * OUT0 ----------------+--|-----------|D0 Q0|-----|<
14 * OUT1 --------------+-|--|-----------|D1 Q1|-----|<
15 * OUT2 ------------+-|-|--|-----------|D2 Q2|-----|<
16 * OUT3 ----------+-|-|-|--|-----------|D3 Q3|-----|<
17 * OUT4 --------+-|-|-|-|--|-----------|D4 Q4|-----|<
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H A Dgpio-eic-sprd.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/gpio/driver.h>
53 * The digital-chip EIC controller can support maximum 3 banks, and each bank
59 #define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
66 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
67 * debounce EIC, latch EIC, async EIC and sync EIC,
70 * (millisecond resolution) and a single-trigger mechanism is introduced
71 * into this sub-module to enhance the input event detection reliability.
74 * The latch EIC is used to latch some special power down signals and
75 * generate interrupts, since the latch EIC does not depend on the APB clock
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H A Dgpio-pcf857x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for pcf857x, pca857x, and pca967x I2C GPIO expanders
8 #include <linux/gpio/driver.h>
59 * that pin be used as an input; it's not an open-drain model, but acts
60 * a bit like one. This is described as "quasi-bidirectional"; read the
63 * Many other I2C GPIO expander chips (like the pca953x models) have
72 unsigned int out; /* software latch */
80 /*-------------------------------------------------------------------------*/
82 /* Talk to 8-bit I/O expander */
94 /* Talk to 16-bit I/O expander */
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H A Dgpio-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/gpio/aspeed.h>
10 #include <linux/gpio/driver.h>
25 * These two headers aren't meant to be used by GPIO drivers. We need
30 #include <linux/gpio/consumer.h>
50 * represents disabled debouncing for the GPIO. Any other value for an element
72 uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch
75 uint16_t rdata_reg; /* Rd: read write latch, Wr: <none> */
85 * line even when the GPIO is configured as an output. Since
89 * The "rdata" register returns the content of the write latch
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H A Dgpio-reg.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * gpio-reg: single register individually fixed-direction GPIOs
18 #include <linux/gpio/driver.h>
19 #include <linux/gpio/gpio-reg.h>
37 return r->direction & BIT(offset) ? GPIO_LINE_DIRECTION_IN : in gpio_reg_get_direction()
46 if (r->direction & BIT(offset)) in gpio_reg_direction_output()
47 return -ENOTSUPP; in gpio_reg_direction_output()
49 gc->set(gc, offset, value); in gpio_reg_direction_output()
57 return r->direction & BIT(offset) ? 0 : -ENOTSUPP; in gpio_reg_direction_input()
66 spin_lock_irqsave(&r->lock, flags); in gpio_reg_set()
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H A Dgpio-amd8111.c1 // SPDX-License-Identifier: GPL-2.0
3 * GPIO driver for AMD 8111 south bridges
5 * Copyright (c) 2012 Dmitry Eremin-Solenikov
28 #include <linux/gpio/driver.h>
37 #define AMD_GPIO_LTCH_STS 0x40 /* Latch status, w1 */
80 agp->orig[offset] = ioread8(agp->pm + AMD_REG_GPIO(offset)) & in amd_gpio_request()
83 dev_dbg(&agp->pdev->dev, "Requested gpio %d, data %x\n", offset, agp->orig[offset]); in amd_gpio_request()
92 dev_dbg(&agp->pdev->dev, "Freed gpio %d, data %x\n", offset, agp->orig[offset]); in amd_gpio_free()
94 iowrite8(agp->orig[offset], agp->pm + AMD_REG_GPIO(offset)); in amd_gpio_free()
103 spin_lock_irqsave(&agp->lock, flags); in amd_gpio_set()
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/openbmc/skeleton/libopenbmc_intf/
H A Dgpio_configs.c9 * http://www.apache.org/licenses/LICENSE-2.0
29 * Loads the GPIO information into the gpios->power_gpio structure
32 * @param gpios - the structure where GpioConfigs.power_gpio will
34 * @param gpio_configs - cJSON pointer to the GPIO JSON
44 /* PGOOD - required */ in read_power_gpios()
49 gpios->power_gpio.power_good_in.name = g_strdup(pgood->valuestring); in read_power_gpios()
51 g_print("Power GPIO power good input: %s\n", in read_power_gpios()
52 gpios->power_gpio.power_good_in.name); in read_power_gpios()
54 /* Latch out - optional */ in read_power_gpios()
56 const cJSON* latch = cJSON_GetObjectItem(power_config, "latch_out"); in read_power_gpios() local
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/openbmc/skeleton/op-pwrctl/
H A Dpower_control_obj.c12 #include <gpio.h>
15 /* ------------------------------------------------------------------------- */
58 g_print("ERROR PowerControl: GPIO open error (gpio=%s,rc=%d)\n", in poll_pgood()
84 GPIO *reset_out = &g_gpio_configs.power_gpio.reset_outs[i]; in poll_pgood()
90 g_print("ERROR PowerControl: GPIO open error (gpio=%s,rc=%d)\n", in poll_pgood()
91 reset_out->name, rc); in poll_pgood()
96 (int)pgood_state, reset_out->name, (int)reset_state); in poll_pgood()
103 GPIO *pci_reset_out = &g_gpio_configs.power_gpio.pci_reset_outs[i]; in poll_pgood()
112 g_print("Holding pci reset: %s\n", pci_reset_out->name); in poll_pgood()
121 g_print("ERROR PowerControl: GPIO open error (gpio=%s,rc=%d)\n", in poll_pgood()
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Darmada3700-xtal-clock.txt4 reading the gpio latch register.
7 of the GPIO block where the gpio latch is located.
8 See Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
11 - compatible : shall be one of the following:
12 "marvell,armada-3700-xtal-clock"
13 - #clock-cells : from common clock binding; shall be set to 0
16 - clock-output-names : from common clock binding; allows overwrite default clock
20 pinctrl_nb: pinctrl-nb@13800 {
21 compatible = "armada3710-nb-pinctrl", "syscon", "simple-mfd";
24 xtalclk: xtal-clk {
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/openbmc/linux/drivers/staging/fbtft/
H A Dfbtft.h1 /* SPDX-License-Identifier: GPL-2.0+ */
23 * struct fbtft_gpio - Structure that holds one pinname to gpio mapping
25 * @gpio: GPIO number
30 struct gpio_desc *gpio; member
36 * struct fbtft_ops - FBTFT operations structure
47 * @request_gpios_match: Do pinname to gpio matching
76 const struct fbtft_gpio *gpio);
88 * struct fbtft_display - Describes the display properties
124 * struct fbtft_platform_data - Passes display specific data to the driver
126 * @gpios: Pointer to an array of pinname to gpio mappings
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/openbmc/u-boot/drivers/gpio/
H A Dpcf8575_gpio.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCF8575 I2C GPIO EXPANDER DRIVER
5 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
10 * Driver for TI PCF-8575 16-bit I2C gpio expander. Based on
11 * gpio-pcf857x Linux Kernel(v4.7) driver.
20 * supports PCF8575 16-bit expander by TI and NXP.
29 #include <asm-generic/gpio.h>
36 /* NOTE: these chips have strange "quasi-bidirectional" I/O pins.
45 * our software copy of the "latch" then matches the chip's all-ones
48 unsigned int out; /* software latch */
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H A Daspeed_gpio.c2 * ast_gpio.c - GPIO driver for the Aspeed SoC
10 #include <asm/gpio.h>
24 uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch
27 uint16_t rdata_reg; /* Rd: read write latch, Wr: <none> */
146 static inline void __iomem *bank_reg(struct aspeed_gpio_priv *gpio, in bank_reg() argument
152 return gpio->regs + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
154 return gpio->regs + bank->rdata_reg; in bank_reg()
156 return gpio->regs + bank->val_regs + GPIO_VAL_DIR; in bank_reg()
158 return gpio->regs + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
160 return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
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/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dfsl-upm-nand.txt4 - compatible : "fsl,upm-nand".
5 - reg : should specify localbus chip select and size used for the chip.
6 - fsl,upm-addr-offset : UPM pattern offset for the address latch.
7 - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
10 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
12 - gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
13 (R/B#). For multi-chip devices, "n" GPIO definitions are required
17 - fsl,upm-wait-flags : add chip-dependent short delays after running the
20 - chip-delay : chip dependent delay for transferring data from array to
24 Each flash chip described may optionally contain additional sub-nodes
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H A Datmel-nand.txt4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
19 - #address-cells: should be set to 2.
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/openbmc/u-boot/include/dm/
H A Dpinctrl.h1 /* SPDX-License-Identifier: GPL-2.0+ */
13 * struct pinconf_param - pin config parameters
27 * struct pinctrl_ops - pin control operations, to be implemented by
47 * in this driver. (necessary for pin-muxing)
50 * certain device to. (necessary for pin-muxing)
54 * may be ignored. (necessary for pin-muxing against a single pin)
59 * (necessary for pin-muxing against a pin group)
60 * @pinconf_num_params: number of driver-specific parameters to be parsed
61 * from device trees (necessary for pin-configuration)
63 * device trees (necessary for pin-configuration)
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,armada-37xx-pinctrl.txt1 * Marvell Armada 37xx SoC pin and gpio controller
3 Each Armada 37xx SoC come with two pin and gpio controller one for the
6 Inside this set of register the gpio latch allows exposing some
11 GPIO and pin controller:
12 ------------------------
16 Refer to pinctrl-bindings.txt in this directory for details of the
22 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
24 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
26 - reg: The first set of register are for pinctrl/gpio and the second
28 - interrupts: list of the interrupt use by the gpio
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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmtk-sd.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
16 - enum:
17 - mediatek,mt2701-mmc
18 - mediatek,mt2712-mmc
19 - mediatek,mt6779-mmc
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/openbmc/linux/include/linux/pinctrl/
H A Dpinconf-generic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
24 * enum pin_config_param - possible pin configuration parameters
25 * @PIN_CONFIG_BIAS_BUS_HOLD: the pin will be set to weakly latch so that it
31 * transition from say pull-up to pull-down implies that you disable
32 * pull-up in the process, this setting disables all biasing.
34 * mode, also know as "third-state" (tristate) or "high-Z" or "floating".
40 * impedance to GROUND). If the argument is != 0 pull-down is enabled,
52 * impedance to VDD). If the argument is != 0 pull-up is enabled,
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/openbmc/linux/arch/m68k/coldfire/
H A Dm53xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * m53xx.c -- platform support for ColdFire 53xx based boards
7 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
38 DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
56 DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
59 DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
60 DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
77 CLKDEV_INIT("imx1-i2c.0", NULL, &__clk_0_22),
94 CLKDEV_INIT("gpio.0", NULL, &__clk_0_41),
97 CLKDEV_INIT("mcfusb-otg.0", NULL, &__clk_0_44),
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/openbmc/linux/arch/m68k/include/asm/
H A Dnettel.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * nettel.h -- Lineo (formerly Moreton Bay) NETtel support.
7 * (C) Copyright 1999-2000, Moreton Bay (www.moretonbay.com)
8 * (C) Copyright 2000-2001, Lineo Inc. (www.lineo.com)
9 * (C) Copyright 2001-2002, SnapGear Inc., (www.snapgear.com)
28 /*---------------------------------------------------------------------------*/
32 * GPIO lines. Most of the LED's are driver through a latch
66 /*---------------------------------------------------------------------------*/
69 * NETtel/5206e based hardware has leds on latch on CS3.
74 /*---------------------------------------------------------------------------*/
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H A Dmcfgpio.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Coldfire generic GPIO support.
12 #include <linux/gpio.h>
15 int __mcfgpio_get_value(unsigned gpio);
16 void __mcfgpio_set_value(unsigned gpio, int value);
17 int __mcfgpio_direction_input(unsigned gpio);
18 int __mcfgpio_direction_output(unsigned gpio, int value);
19 int __mcfgpio_request(unsigned gpio);
20 void __mcfgpio_free(unsigned gpio);
23 static inline int __gpio_get_value(unsigned gpio) in __gpio_get_value() argument
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/openbmc/docs/designs/
H A Ddevice-tree-gpio-naming.md1 # Device Tree GPIO Naming in OpenBMC
11 The Linux kernel has deprecated the use of sysfs to interact with the GPIO
12 subsystem. The replacement is a "descriptor-based" character device interface.
15 provides an abstraction to this new character device gpio interface.
19 for these GPIO names and if you want userspace code to be able to be consistent
24 The kernel [documentation][2] has a good summary of the GPIO subsystem. The
25 specific field used to name the GPIOs in the DTS is `gpio-line-names`. This
29 scheme in the face of a universe of potential use-cases.
37 - Ensure common function GPIOs within OpenBMC use the same naming convention
42 naming convention and then the sub bullets list the common GPIO names to be used
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/openbmc/linux/drivers/irqchip/
H A Dirq-aspeed-vic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015 - Ben Herrenschmidt, IBM Corp.
7 * Based on irq-vic.c:
9 * Copyright (C) 1999 - 2003 ARM Limited
63 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR); in vic_init_hw()
64 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4); in vic_init_hw()
67 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR); in vic_init_hw()
68 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4); in vic_init_hw()
71 writel(0, vic->base + AVIC_INT_SELECT); in vic_init_hw()
72 writel(0, vic->base + AVIC_INT_SELECT + 4); in vic_init_hw()
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