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/openbmc/u-boot/arch/arm/dts/
H A Ds5pc110-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * U-Boot additions to enable a generic Exynos GPIO driver
10 #address-cells = <1>;
11 #size-cells = <1>;
13 gpio-controller;
14 #gpio-cells = <2>;
18 gpio-controller;
19 #gpio-cells = <2>;
23 gpio-controller;
24 #gpio-cells = <2>;
[all …]
H A Dexynos5250-pinctrl.dtsi2 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
7 * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device
18 gpio-controller;
19 #gpio-cells = <2>;
21 interrupt-controller;
22 #interrupt-cells = <2>;
26 gpio-controller;
27 #gpio-cells = <2>;
29 interrupt-controller;
30 #interrupt-cells = <2>;
[all …]
H A Dexynos4x12-pinctrl.dtsi2 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
7 * Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device
18 gpio-controller;
19 #gpio-cells = <2>;
21 interrupt-controller;
22 #interrupt-cells = <2>;
26 gpio-controller;
27 #gpio-cells = <2>;
29 interrupt-controller;
30 #interrupt-cells = <2>;
[all …]
H A Ds5pc100-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * U-Boot additions to enable a generic Exynos GPIO driver
11 gpio-controller;
12 #gpio-cells = <2>;
16 gpio-controller;
17 #gpio-cells = <2>;
21 gpio-controller;
22 #gpio-cells = <2>;
26 gpio-controller;
27 #gpio-cells = <2>;
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H A Dexynos4210-pinctrl.dtsi2 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
4 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
6 * Copyright (c) 2011-2012 Linaro Ltd.
9 * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
20 gpio-controller;
21 #gpio-cells = <2>;
23 interrupt-controller;
24 #interrupt-cells = <2>;
28 gpio-controller;
29 #gpio-cells = <2>;
[all …]
H A Dexynos54xx-pinctrl.dtsi2 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
7 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
15 #include "exynos54xx-pinctrl-uboot.dtsi"
20 gpio-controller;
21 #gpio-cells = <2>;
23 interrupt-controller;
24 #interrupt-cells = <2>;
28 gpio-controller;
29 #gpio-cells = <2>;
31 interrupt-controller;
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H A Dstm32mp157-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
10 pinctrl: pin-controller@50002000 {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "st,stm32mp157-pinctrl";
15 interrupt-parent = <&exti>;
17 pins-are-numbered;
19 gpioa: gpio@50002000 {
[all …]
H A Dkeystone-k2hk.dtsi2 * Copyright 2013-2014 Texas Instruments, Inc.
13 #address-cells = <1>;
14 #size-cells = <0>;
16 interrupt-parent = <&gic>;
19 compatible = "arm,cortex-a15";
25 compatible = "arm,cortex-a15";
31 compatible = "arm,cortex-a15";
37 compatible = "arm,cortex-a15";
44 /include/ "keystone-k2hk-clocks.dtsi"
47 compatible = "ti,keystone-dsp-gpio";
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H A Dimx53.dtsi10 * http://www.opensource.org/licenses/gpl-license.html
15 #include "imx53-pinfunc.h"
16 #include <dt-bindings/clock/imx5-clock.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/input/input.h>
19 #include <dt-bindings/interrupt-controller/irq.h>
38 tzic: tz-interrupt-controller@fffc000 {
39 compatible = "fsl,imx53-tzic", "fsl,tzic";
40 interrupt-controller;
41 #interrupt-cells = <1>;
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H A Dstm32h743-pinctrl.dtsi2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/pinctrl/stm32h7-pinfunc.h>
47 pin-controller {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "st,stm32h743-pinctrl";
52 pins-are-numbered;
54 gpioa: gpio@58020000 {
55 gpio-controller;
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H A Dhi3798cv200.dtsi4 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
7 * SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/clock/histb-clock.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/reset/ti-syscon.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
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H A Dr8a77990.dtsi1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a77990-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a53", "arm,armv8";
25 power-domains = <&sysc 5>;
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/openbmc/u-boot/doc/device-tree-bindings/gpio/
H A Dgpio.txt1 Specifying GPIO information for devices
5 -----------------
8 properties, each containing a 'gpio-list':
10 gpio-list ::= <single-gpio> [gpio-list]
11 single-gpio ::= <gpio-phandle> <gpio-specifier>
12 gpio-phandle : phandle to gpio controller node
13 gpio-specifier : Array of #gpio-cells specifying specific gpio
14 (controller specific)
16 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
17 of this GPIO for the device. While a non-existent <name> is considered valid
[all …]
H A Dnvidia,tegra186-gpio.txt1 NVIDIA Tegra186 GPIO controllers
3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
4 controller. This binding document applies to both controllers. The register
9 The Tegra186 GPIO controller allows software to set the IO direction of, and
10 read/write the value of, numerous GPIO signals. Routing of GPIO signals to
11 package balls is under the control of a separate pin controller HW block. Two
14 a) Security registers, which allow configuration of allowed access to the GPIO
17 varies between the different GPIO controllers.
20 that wishes to configure access to the GPIO registers needs access to these
21 registers to do so. Code which simply wishes to read or write GPIO data does not
[all …]
H A Dgpio-samsung.txt1 Samsung Exynos4 GPIO Controller
4 - compatible: Compatible property value should be "samsung,exynos4-gpio>".
6 - reg: Physical base address of the controller and length of memory mapped
9 - #gpio-cells: Should be 4. The syntax of the gpio specifier used by client nodes
11 <[phandle of the gpio controller node]
12 [pin number within the gpio controller]
17 Values for gpio specifier:
18 - Pin number: is a value between 0 to 7.
19 - Flags and Pull Up/Down: 0 - Pull Up/Down Disabled.
20 1 - Pull Down Enabled.
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H A Dnvidia,tegra20-gpio.txt1 NVIDIA Tegra GPIO controller
4 - compatible : "nvidia,tegra<chip>-gpio"
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller. For Tegra20,
9 - #gpio-cells : Should be two. The first cell is the pin number and the
11 - bit 0 specifies polarity (0 for normal, 1 for inverted)
12 - gpio-controller : Marks the device node as a GPIO controller.
13 - #interrupt-cells : Should be 2.
14 The first cell is the GPIO number.
17 1 = low-to-high edge triggered.
[all …]
H A Dgpio-msm.txt1 Qualcomm Snapdragon GPIO controller
4 - compatible : "qcom,msm8916-pinctrl" or "qcom,apq8016-pinctrl"
5 - reg : Physical base address and length of the controller's registers.
6 This controller is called "Top Level Mode Multiplexing" in
8 - #gpio-cells : Should be one (pin number).
9 - gpio-controller : Marks the device node as a GPIO controller.
10 - gpio-count: Number of GPIO pins.
11 - gpio-bank-name: (optional) name of gpio bank. As default "soc" is used.
16 compatible = "qcom,msm8916-pinctrl";
18 gpio-controller;
[all …]
H A Dgpio-pcf857x.txt1 * PCF857x-compatible I/O expanders
3 The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be
4 driven high by a pull-up current source or driven low to ground. This combines
14 - compatible: should be one of the following.
15 - "maxim,max7328": For the Maxim MAX7378
16 - "maxim,max7329": For the Maxim MAX7329
17 - "nxp,pca8574": For the NXP PCA8574
18 - "nxp,pca8575": For the NXP PCA8575
19 - "nxp,pca9670": For the NXP PCA9670
20 - "nxp,pca9671": For the NXP PCA9671
[all …]
H A Dmscc_sgpio.txt1 Microsemi Corporation (MSCC) Serial GPIO driver
3 The MSCC serial GPIO extends the number or GPIO's on the system by
6 effective GPIO count can be extended by up to 128 GPIO's per
7 controller.
10 - compatible : "mscc,luton-sgpio" or "mscc,ocelot-sgpio"
11 - clock: Reference clock used to generate clock divider setting. See
12 mscc,sgpio-frequency property.
13 - reg : Physical base address and length of the controller's registers.
14 - #gpio-cells : Should be two. The first cell is the pin number and the
16 - bit 0 specifies polarity (0 for normal, 1 for inverted)
[all …]
H A Dpm8916_gpio.txt1 Driver for part of pm8916 PMIC - gpio and power/reset keys
5 1) GPIO driver
8 - compatible: "qcom,pm8916-gpio"
9 - reg: peripheral ID, size of register block
10 - gpio-controller
11 - gpio-count: number of GPIOs
12 - #gpio-cells: 2
15 - gpio-bank-name: name of bank (as default "pm8916" is used)
20 compatible = "qcom,pm8916-gpio";
22 gpio-controller;
[all …]
/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Drockchip,pinctrl.txt1 * Rockchip Pinmux Controller
3 The Rockchip Pinmux Controller, enables the IC
6 muxing options with option 0 being the use as a GPIO.
8 Please refer to pinctrl-bindings.txt in this directory for details of the
16 settings such as pull-up, etc.
19 defined as gpio sub-nodes of the pinmux controller.
21 Required properties for iomux controller:
22 - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
23 "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
24 "rockchip,rk3288-pinctrl"
[all …]
H A Dmarvell,armada-37xx-pinctrl.txt1 * Marvell Armada 37xx SoC pin and GPIO controller
3 Each Armada 37xx SoC comes with two pin and GPIO controllers, one for the
6 GPIO and pin controller:
7 ------------------------
11 Refer to pinctrl-bindings.txt in this directory for details of the
17 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
19 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
21 - reg: The first set of registers is for pinctrl/GPIO and the second
22 set is for the interrupt controller
23 - interrupts: list of interrupts used by the GPIO
[all …]
H A Dst,stm32-pinctrl.txt1 * STM32 GPIO and Pin Mux/Config controller
3 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
4 controller. It controls the input/output settings on the available pins and
5 also provides ability to multiplex and configure the output of various on-chip
8 Pin controller node:
10 - compatible: value should be one of the following:
11 (a) "st,stm32f429-pinctrl"
12 (b) "st,stm32f746-pinctrl"
13 - #address-cells: The value of this property must be 1
14 - #size-cells : The value of this property must be 1
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dpic32mzda.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/microchip,clock.h>
9 #include <dt-bindings/gpio/gpio.h>
35 compatible = "microchip,pic32mzda-clk";
37 #clock-cells = <1>;
41 compatible = "microchip,pic32mzda-uart";
49 compatible = "microchip,pic32mzda-uart";
57 compatible = "microchip,pic32mzda-uart";
64 evic: interrupt-controller@1f810000 {
[all …]
/openbmc/u-boot/drivers/gpio/
H A DKconfig2 # GPIO infrastructure and drivers
5 menu "GPIO Support"
8 bool "Enable Driver Model for GPIO drivers"
11 Enable driver model for GPIO access. The standard GPIO
13 the GPIO uclass. Drivers provide methods to query the
15 is defined in include/asm-generic/gpio.h.
18 bool "Enable GPIO hog support"
22 Enable gpio hog support
23 The GPIO chip may contain GPIO hog definitions. GPIO hogging
24 is a mechanism providing automatic GPIO request and config-
[all …]

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