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/openbmc/linux/drivers/gpu/drm/amd/display/dc/basics/
H A Dfixpt31_32.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
39 return (unsigned long long)(-arg); in abs_i64()
63 ((1ULL << FIXED31_32_BITS_PER_FRACTIONAL_PART) - 1)
78 unsigned long long arg1_value = arg1_negative ? -numerator : numerator; in dc_fixpt_from_fraction()
79 unsigned long long arg2_value = arg2_negative ? -denominator : denominator; in dc_fixpt_from_fraction()
90 /* determine fractional part */ in dc_fixpt_from_fraction()
101 remainder -= arg2_value; in dc_fixpt_from_fraction()
103 } while (--i != 0); in dc_fixpt_from_fraction()
110 ASSERT(res_value <= LLONG_MAX - summand); in dc_fixpt_from_fraction()
118 res.value = -res.value; in dc_fixpt_from_fraction()
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/openbmc/u-boot/include/
H A Dvideo_console.h1 /* SPDX-License-Identifier: GPL-2.0+ */
41 * struct vidconsole_priv - uclass-private data about a console device
47 * @xcur_frac: Current X position, in fractional units (VID_TO_POS(x))
53 * @tab_width_frac: Tab width in fractional units
54 * @xsize_frac: Width of the display in fractional units
55 * @xstart_frac: Left margin for the text console in fractional units
59 * @col_saved: Saved X position, in fractional units (VID_TO_POS(x))
88 * struct vidconsole_ops - Video console operations
92 * of an entire line of text - typically 16 pixels).
96 * putc_xy() - write a single character to a position
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/openbmc/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Dspl_mem_init.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
94 debug("SPL: Using default SDRAM parameters\n"); in mxs_adjust_memory_params()
102 debug("SPL: Setting mx28 board specific SDRAM parameters\n"); in initialize_dram_values()
105 debug("SPL: Applying SDRAM parameters\n"); in initialize_dram_values()
114 debug("SPL: Setting mx23 board specific SDRAM parameters\n"); in initialize_dram_values()
126 debug("SPL: Applying SDRAM parameters\n"); in initialize_dram_values()
146 /* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */ in mxs_mem_init_clock()
149 /* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */ in mxs_mem_init_clock()
153 debug("SPL: Initialising FRAC0\n"); in mxs_mem_init_clock()
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/openbmc/linux/drivers/clk/spear/
H A Dclk-frac-synth.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Fractional Synthesizer clock implementation
9 #define pr_fmt(fmt) "clk-frac-synth: " fmt
11 #include <linux/clk-provider.h>
20 * DOC: Fractional Synthesizer clock
25 * div is 17 bits:-
26 * 0-13 (fractional part)
27 * 14-16 (integer part)
28 * div is (16-14 bits).(13-0 bits) (in binary)
45 struct frac_rate_tbl *rtbl = frac->rtbl; in frac_calc_rate()
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/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu_frac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
16 if (!(common->features & CCU_FEATURE_FRACTIONAL)) in ccu_frac_helper_is_enabled()
19 return !(readl(common->base + common->reg) & cf->enable); in ccu_frac_helper_is_enabled()
29 if (!(common->features & CCU_FEATURE_FRACTIONAL)) in ccu_frac_helper_enable()
32 spin_lock_irqsave(common->lock, flags); in ccu_frac_helper_enable()
33 reg = readl(common->base + common->reg); in ccu_frac_helper_enable()
34 writel(reg & ~cf->enable, common->base + common->reg); in ccu_frac_helper_enable()
35 spin_unlock_irqrestore(common->lock, flags); in ccu_frac_helper_enable()
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/openbmc/linux/drivers/clk/zynqmp/
H A Ddivider.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Xilinx
11 #include <linux/clk-provider.h>
13 #include "clk-zynqmp.h"
19 * prepare - clk_prepare only ensures that parents are prepared
20 * enable - clk_enable only ensures that parents are enabled
21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
22 * parent - fixed parent. No clk_set_parent support
28 #define CLK_FRAC BIT(13) /* has a fractional parent */
29 #define CUSTOM_FLAG_CLK_FRAC BIT(0) /* has a fractional parent in custom type flag */
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/openbmc/linux/drivers/hwmon/
H A Demc2103.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * emc2103.c - Support for SMSC EMC2103
13 #include <linux/hwmon-sysfs.h>
39 * 2103-2 and 2103-4's 3rd temperature sensor can be connected to two diodes
40 * in anti-parallel mode, and in this configuration both can be read
43 * it. Default is to leave the device in the state it's already in (-1).
46 static int apd = -1;
48 MODULE_PARM_DESC(apd, "Set to zero to disable anti-parallel diode mode");
52 u8 fraction; /* 0-7 multiples of 0.125 */
64 s8 temp_min[4]; /* no fractional part */
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/openbmc/linux/sound/soc/tegra/
H A Dtegra186_asrc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra186_asrc.c - Tegra186 ASRC driver
74 regmap_write(asrc->regmap, in tegra186_asrc_lock_stream()
84 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_runtime_suspend()
85 regcache_mark_dirty(asrc->regmap); in tegra186_asrc_runtime_suspend()
95 regcache_cache_only(asrc->regmap, false); in tegra186_asrc_runtime_resume()
102 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, in tegra186_asrc_runtime_resume()
104 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB, in tegra186_asrc_runtime_resume()
107 regcache_sync(asrc->regmap); in tegra186_asrc_runtime_resume()
110 if (asrc->lane[id].ratio_source != in tegra186_asrc_runtime_resume()
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/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3328.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
18 #include <dt-bindings/clock/rk3328-cru.h>
29 ((input_rate) / (output_rate) - 1);
193 * Formulas also embedded within the Fractional PLL Verilog model:
198 * FOUTVCO = Fractional PLL non-divided output frequency
199 * FOUTPOSTDIV = Fractional PLL divided output frequency
201 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
202 * REFDIV = Fractional PLL input reference clock divider
216 pll_con = cru->apll_con; in rkclk_set_pll()
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/openbmc/linux/drivers/rtc/
H A Drtc-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
47 #define RTC_MIN_OFFSET -32768000
71 writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); in xlnx_rtc_set_time()
81 writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_set_time()
92 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_read_time()
99 read_time = readl(xrtcdev->reg_base + RTC_CUR_TM); in xlnx_rtc_read_time()
105 * Since we add +1 sec while writing, we need to -1 sec while in xlnx_rtc_read_time()
108 read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1; in xlnx_rtc_read_time()
119 rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time); in xlnx_rtc_read_alarm()
120 alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM; in xlnx_rtc_read_alarm()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_abm.c2 * Copyright 2012-16 Advanced Micro Devices, Inc.
41 (abm_dce->regs->reg)
45 abm_dce->abm_shift->field_name, abm_dce->abm_mask->field_name
48 abm->ctx->logger
50 abm_dce->base.ctx
63 if (abm->dmcu_is_running == false) in dce_abm_set_pipe()
100 // Take MSB of fractional part since backlight is not max in dmcu_set_backlight_level()
103 dce_abm_set_pipe(&abm_dce->base, controller_id, panel_id); in dmcu_set_backlight_level()
183 * 1 bit integer and 16 bit fractional in dce_abm_get_current_backlight()
194 * 1 bit integer and 16 bit fractional in dce_abm_get_target_backlight()
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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_pll.c33 * amdgpu_pll_reduce_ratio - fractional number reduction
70 * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation
91 if (adev->family == AMDGPU_FAMILY_SI) in amdgpu_pll_get_fb_ref_div()
108 * amdgpu_pll_compute - compute PLL paramaters
115 * @frac_fb_div_p: fractional part of the feedback divider
131 unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ? in amdgpu_pll_compute()
141 fb_div_min = pll->min_feedback_div; in amdgpu_pll_compute()
142 fb_div_max = pll->max_feedback_div; in amdgpu_pll_compute()
144 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) { in amdgpu_pll_compute()
150 if (pll->flags & AMDGPU_PLL_USE_REF_DIV) in amdgpu_pll_compute()
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/openbmc/linux/sound/soc/codecs/
H A Dadau-utils.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2011-2016 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
13 #include "adau-utils.h"
18 unsigned int r, n, m, i, j; in adau_calc_pll_cfg() local
23 n = 0; in adau_calc_pll_cfg()
33 n = i / j; in adau_calc_pll_cfg()
35 div--; in adau_calc_pll_cfg()
38 n = 0; in adau_calc_pll_cfg()
42 if (n > 0xffff || m > 0xffff || div > 3 || r > 8 || r < 2) in adau_calc_pll_cfg()
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/openbmc/linux/drivers/clk/rockchip/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
19 #include <linux/clk-provider.h>
25 #include "../clk-fractional-divider.h"
32 * src1 --|--\
33 * |M |--[GATE]-[DIV]-
34 * src2 --|--/
59 return ERR_PTR(-ENOMEM); in rockchip_clk_register_branch()
61 mux->reg = base + muxdiv_offset; in rockchip_clk_register_branch()
62 mux->shift = mux_shift; in rockchip_clk_register_branch()
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/openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.h1 /* SPDX-License-Identifier: GPL-2.0+ */
13 printf("Write [0x%p] = 0x%08x\n", addr, val); in writel()
20 printf("Read [0x%p] = 0x%08x\n", addr, val); in readl()
37 * struct clk_ops - standard clock operations
79 #define BAD_CLK_NAME ((const char *)-1)
88 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
89 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
90 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
91 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
107 (div)->frac_width > 0)
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/openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.h1 /* SPDX-License-Identifier: GPL-2.0+ */
13 printf("Write [0x%p] = 0x%08x\n", addr, val); in writel()
20 printf("Read [0x%p] = 0x%08x\n", addr, val); in readl()
37 * struct clk_ops - standard clock operations
79 #define BAD_CLK_NAME ((const char *)-1)
88 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
89 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
90 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
91 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
107 (div)->frac_width > 0)
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/openbmc/linux/drivers/clk/renesas/
H A Drcar-gen4-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen4 Clock Pulse Generator
7 * Based on rcar-gen3-cpg.c
9 * Copyright (C) 2015-2018 Glider bvba
15 #include <linux/clk-provider.h>
23 #include "renesas-cpg-mssr.h"
24 #include "rcar-gen4-cpg.h"
25 #include "rcar-cpg-lib.h"
33 #define CPG_PLLECR_PLLST(n) BIT(8 + ((n) < 3 ? (n) - 1 : \ argument
34 (n) > 3 ? (n) + 1 : n)) /* PLLn Circuit Status */
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/openbmc/linux/drivers/clk/
H A Dclk-fractional-divider.c1 // SPDX-License-Identifier: GPL-2.0
5 * Adjustable fractional divider clock implementation.
10 * rate = (m / n) * parent_rate (1)
13 * m (numerator) and n (denominator) values to be provided to satisfy
16 * Since m and n have the limitation by a range, e.g.
18 * n >= 1, n < N_width, where N_width = 2^nwidth (2)
32 * scale = floor(log2(parent_rate / rate)) - nwidth (5)
34 * and assume that the IP, that needs m and n, has also its own
37 * at the same time a much better result of m and n than simple
49 #include <linux/clk-provider.h>
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H A Dclk-plldig.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
48 * Denominator part of the fractional part of the
70 val = readl(data->regs + PLLDIG_REG_PLLFM); in plldig_enable()
76 writel(val, data->regs + PLLDIG_REG_PLLFM); in plldig_enable()
86 val = readl(data->regs + PLLDIG_REG_PLLFM); in plldig_disable()
91 writel(val, data->regs + PLLDIG_REG_PLLFM); in plldig_disable()
98 return readl(data->regs + PLLDIG_REG_PLLFM) & in plldig_is_enabled()
108 val = readl(data->regs + PLLDIG_REG_PLLDV); in plldig_recalc_rate()
123 return DIV_ROUND_UP(data->vco_freq, rfdphi1); in plldig_recalc_rate()
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H A Dclk-si544.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
74 * struct clk_si544_muldiv - Multiplier/divider settings
76 * @fb_div_int: fractional part of feedback divider (11 bits)
79 * If ls_div_bits is non-zero, hs_div must be even
80 * @delta_m: Frequency shift for small -950..+950 ppm changes, 24 bit
93 return regmap_update_bits(data->regmap, SI544_REG_OE_STATE, in si544_enable_output()
117 err = regmap_read(data->regmap, SI544_REG_OE_STATE, &val); in si544_is_prepared()
131 err = regmap_bulk_read(data->regmap, SI544_REG_HS_DIV, reg, 2); in si544_get_muldiv()
135 settings->ls_div_bits = (reg[1] >> 4) & 0x07; in si544_get_muldiv()
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/openbmc/u-boot/cmd/
H A Dmisc.c1 // SPDX-License-Identifier: GPL-2.0+
35 mdelay += (*frpart - '0') * mult; in do_sleep()
44 return (-1); in do_sleep()
55 "N\n"
56 " - delay execution for N seconds (N is _decimal_ and can be\n"
57 " fractional)"
73 printf("%ld.%03d\n", msecs / 1000, (int)(msecs % 1000)); in do_timer()
82 "start - Reset the timer reference.\n"
83 "timer get - Print the time since 'start'."
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-frequency-adf43503 Contact: linux-iio@vger.kernel.org
7 the fractional-N PLL. It is assumed that the algorithm
13 Contact: linux-iio@vger.kernel.org
/openbmc/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,admv4420.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nuno Sá <nuno.sa@analog.com>
14 mixer with an integrated fractional-N synthesizer, ideally suited
20 - adi,admv4420
25 spi-max-frequency:
28 adi,lo-freq-khz:
32 adi,ref-ext-single-ended-en:
37 - compatible
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/openbmc/qemu/disas/
H A Dcapstone.c3 * SPDX-License-Identifier: GPL-2.0-or-later
8 #include "disas/dis-asm.h"
59 * re-open the target handle with a different arch for the target in order
64 cs_mode cap_mode = info->cap_mode; in cap_disas_start()
67 cap_mode += (info->endian == BFD_ENDIAN_BIG ? CS_MODE_BIG_ENDIAN in cap_disas_start()
70 err = cs_open(info->cap_arch, cap_mode, handle); in cap_disas_start()
78 switch (info->cap_arch) { in cap_disas_start()
106 int i, int n) in cap_dump_insn_units() argument
108 fprintf_function print = info->fprintf_func; in cap_dump_insn_units()
109 FILE *stream = info->stream; in cap_dump_insn_units()
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/openbmc/linux/arch/arm/include/asm/
H A Ddelay.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 1995-2004 Russell King
5 * Delay routines, using a pre-computed "loops_per_second" value.
24 * fractional number. To make this usable with integer math, we
58 #define __delay(n) arm_delay_ops.delay(n) argument
79 #define __udelay(n) arm_delay_ops.udelay(n) argument
80 #define __const_udelay(n) arm_delay_ops.const_udelay(n) argument
82 #define udelay(n) \ argument
83 (__builtin_constant_p(n) ? \
84 ((n) > (MAX_UDELAY_MS * 1000) ? __bad_udelay() : \
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