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/openbmc/u-boot/arch/arm/dts/
H A Dam33xx-clocks.dtsi2 * Device Tree Source for AM33xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
15 ti,bit-shift = <22>;
20 #clock-cells = <0>;
21 compatible = "fixed-factor-clock";
23 clock-mult = <1>;
24 clock-div = <1>;
28 #clock-cells = <0>;
29 compatible = "fixed-factor-clock";
[all …]
H A Dam43xx-clocks.dtsi2 * Device Tree Source for AM43xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
15 ti,bit-shift = <31>;
20 #clock-cells = <0>;
21 compatible = "ti,mux-clock";
23 ti,bit-shift = <29>;
28 #clock-cells = <0>;
29 compatible = "ti,mux-clock";
31 ti,bit-shift = <22>;
[all …]
H A Domap36xx-omap3430es2plus-clocks.dtsi2 * Device Tree Source for OMAP34xx/OMAP36xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,composite-no-wait-gate-clock";
15 ti,bit-shift = <0>;
20 #clock-cells = <0>;
21 compatible = "ti,composite-divider-clock";
23 ti,bit-shift = <8>;
29 #clock-cells = <0>;
30 compatible = "ti,composite-clock";
35 #clock-cells = <0>;
[all …]
H A Dzynqmp-clk.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Clock specification for Xilinx ZynqMP
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <100000000>;
15 u-boot,dm-pre-reloc;
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <125000000>;
[all …]
H A Domap3xxx-clocks.dtsi2 * Device Tree Source for OMAP3 clock data
12 #clock-cells = <0>;
13 compatible = "fixed-clock";
14 clock-frequency = <16800000>;
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
25 #clock-cells = <0>;
26 compatible = "ti,divider-clock";
28 ti,bit-shift = <6>;
29 ti,max-div = <3>;
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm11351.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2012-2013 Broadcom Corporation
4 #include <dt-bindings/clock/bcm281xx.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
13 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <0>;
[all …]
H A Dbcm21664.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <dt-bindings/clock/bcm21664.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
13 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a9";
[all …]
H A Dbcm23550.dtsi34 #include <dt-bindings/clock/bcm21664.h>
35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/interrupt-controller/irq.h>
39 #address-cells = <1>;
40 #size-cells = <1>;
43 interrupt-parent = <&gic>;
46 #address-cells = <1>;
47 #size-cells = <0>;
51 compatible = "arm,cortex-a7";
53 clock-frequency = <1000000000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dnuvoton,npcm750-clk.txt1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
8 There are six fixed clocks that are generated outside the BMC. All clocks are of
9 a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and
10 clk_sysbypck are inputs to the clock controller.
12 network. They are set on the device tree, but not used by the clock module. The
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
[all …]
H A Dcirrus,lochnagar.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/cirrus,lochnagar.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
15 Logic devices on mini-cards, as well as allowing connection of various
21 This binding document describes the binding for the clock portion of the
25 [1] Clock : ../clock/clock-bindings.txt
28 [2] include/dt-bindings/clock/lochnagar.h
36 - cirrus,lochnagar1-clk
[all …]
H A Dfixed-factor-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed factor rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - fixed-factor-clock
18 "#clock-cells":
24 clock-div:
[all …]
/openbmc/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-clks.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <100000000>;
12 clock-output-names = "adl3clk_100mhz";
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <375000000>;
19 clock-output-names = "ccpclk_375mhz";
23 compatible = "fixed-clock";
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam33xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for AM33xx clock data
8 sys_clkin_ck: clock-sys-clkin-22@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <22>;
17 adc_tsc_fck: clock-adc-tsc-fck {
18 #clock-cells = <0>;
19 compatible = "fixed-factor-clock";
[all …]
H A Ddm814x-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <1>;
11 compatible = "ti,dm814-adpll-s-clock";
14 clock-names = "clkinp", "clkinpulow", "clkinphif";
15 clock-output-names = "481c5040.adpll.dcoclkldo",
22 #clock-cells = <1>;
23 compatible = "ti,dm814-adpll-lj-clock";
26 clock-names = "clkinp", "clkinpulow";
27 clock-output-names = "481c5080.adpll.dcoclkldo",
33 #clock-cells = <1>;
[all …]
H A Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for AM43xx clock data
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
[all …]
H A Domap36xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP34xx/OMAP36xx clock data
8 clock@a00 {
11 #clock-cells = <2>;
12 #address-cells = <0>;
14 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 {
15 #clock-cells = <0>;
16 compatible = "ti,composite-no-wait-gate-clock";
17 clock-output-names = "ssi_ssr_gate_fck_3430es2";
19 ti,bit-shift = <0>;
[all …]
H A Ddra7xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for DRA7xx clock data
8 atl_clkin0_ck: clock-atl-clkin0 {
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
11 clock-output-names = "atl_clkin0_ck";
15 atl_clkin1_ck: clock-atl-clkin1 {
16 #clock-cells = <0>;
17 compatible = "ti,dra7-atl-clock";
18 clock-output-names = "atl_clkin1_ck";
[all …]
/openbmc/linux/drivers/clk/
H A Dclk-fixed-rate.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 * Fixed rate clock implementation
9 #include <linux/clk-provider.h>
18 * DOC: basic fixed-rate clock that cannot gate
20 * Traits of this clock:
21 * prepare - clk_(un)prepare only ensures parents are prepared
22 * enable - clk_enable only ensures parents are enabled
23 * rate - rate is always a fixed value. No clk_set_rate support
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/axm/
H A Daxm5516-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/boot/dts/axm5516-cpus.dtsi
10 #address-cells = <1>;
11 #size-cells = <0>;
13 cpu-map {
74 compatible = "arm,cortex-a15";
76 clock-frequency = <1400000000>;
77 cpu-release-addr = <0>; // Fixed by the boot loader
82 compatible = "arm,cortex-a15";
84 clock-frequency = <1400000000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Djuno-clocks.dtsi4 * Copyright (c) 2013-2014 ARM Ltd
10 /* SoC fixed clocks */
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <7372800>;
15 clock-output-names = "juno:uartclk";
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <48000000>;
22 clock-output-names = "clk48mhz";
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for Keystone 2 clock tree
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #clock-cells = <0>;
15 compatible = "ti,keystone,pll-mux-clock";
18 bit-shift = <23>;
19 bit-mask = <1>;
20 clock-output-names = "mainmuxclk";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/ti/
H A Dfixed-factor-clock.txt1 Binding for TI fixed factor rate clock sources.
3 Binding status: Unstable - ABI compatibility may be broken in the future
5 This binding uses the common clock binding[1], and also uses the autoidle
6 support from TI autoidle clock [2].
8 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 [2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
12 - compatible : shall be "ti,fixed-factor-clock".
13 - #clock-cells : from common clock binding; shall be set to 0.
14 - ti,clock-div: fixed divider.
15 - ti,clock-mult: fixed multiplier.
[all …]
/openbmc/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-clock.dtsi4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/clock/bcm-sr.h>
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
38 clock-frequency = <50000000>;
42 #clock-cells = <0>;
43 compatible = "fixed-factor-clock";
45 clock-div = <2>;
46 clock-mult = <1>;
50 #clock-cells = <1>;
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dmps2.dtsi6 * This file is dual-licensed: you can use it either under the terms
45 #include "../armv7-m.dtsi"
48 #address-cells = <1>;
49 #size-cells = <1>;
51 oscclk0: clk-osc0 {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <50000000>;
57 oscclk1: clk-osc1 {
58 compatible = "fixed-clock";
[all …]
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dfixed-factor-clock.txt1 Binding for simple fixed factor rate clock sources.
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be "fixed-factor-clock".
9 - #clock-cells : from common clock binding; shall be set to 0.
10 - clock-div: fixed divider.
11 - clock-mult: fixed multiplier.
12 - clocks: parent clock.
15 - clock-output-names : From common clock binding.
18 clock {
[all …]

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