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/openbmc/qemu/hw/audio/
H A Dtrace-events6 cs4231_mem_writel_reg(uint32_t reg, uint32_t old, uint32_t val) "write reg %d: 0x%08x -> 0x%08x"
7 cs4231_mem_writel_dreg(uint32_t reg, uint32_t old, uint32_t val) "write dreg %d: 0x%02x -> 0x%02x"
12 es1370_frame_count_rd(int ch, uint32_t curr, uint32_t size) "ch=%d CURR_CT=%u BUF_SIZE=%u"
13 es1370_frame_count_wr(int ch, uint32_t curr, uint32_t size) "ch=%d CURR_CT=%u BUF_SIZE=%u"
20 # hda-codec.c
26 #via-ac97.c
27 via_ac97_codec_write(uint8_t addr, uint16_t val) "0x%x <- 0x%x"
29 via_ac97_sgd_read(uint64_t addr, unsigned size, uint64_t val) "0x%"PRIx64" %d -> 0x%"PRIx64
30 via_ac97_sgd_write(uint64_t addr, unsigned size, uint64_t val) "0x%"PRIx64" %d <- 0x%"PRIx64
33 asc_read_fifo(const char fifo, int reg, unsigned size, uint64_t value) "fifo %c reg=0x%03x size=%u …
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H A Dasc.c7 * Copyright (c) 2012-2018 Laurent Vivier <laurent@vivier.eu>
8 * Copyright (c) 2022 Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
10 * SPDX-License-Identifier: GPL-2.0-or-later
20 #include "hw/qdev-properties.h"
37 * 1=FIFO mode,
43 * 0x803: FIFO MODE
44 * bit 7=clear FIFO,
45 * bit 1="non-ROM companding",
47 * 0x804: FIFO IRQ STATUS
53 * bits 0-3 wavetables 0-3 start
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H A Dpl041.c5 * Written by Mathieu Sonet - www.elasticsheep.com
15 * - Supports only a playback on one channel (Versatile/Vexpress)
16 * - Supports only one TX FIFO in compact-mode or non-compact mode.
17 * - Supports playback of 12, 16, 18 and 20 bits samples.
18 * - Record is not supported.
19 * - The PL041 is hardwired to a LM4549 codec.
25 #include "hw/qdev-properties.h"
61 /* This FIFO only stores 20-bit samples on 32-bit words.
89 uint32_t fifo_depth; /* FIFO depth in non-compact mode */
125 /* Add the fifo depth information */ in pl041_compute_periphid3()
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/openbmc/qemu/hw/net/
H A Dallwinner_emac.c7 * This model is based on reverse-engineering of Linux kernel driver.
27 #include "hw/qdev-properties.h"
37 mii->bmsr |= MII_BMSR_LINK_ST | MII_BMSR_AN_COMP; in mii_set_link()
38 mii->anlpar |= MII_ANAR_TXFD | MII_ANAR_10FD | MII_ANAR_10 | in mii_set_link()
41 mii->bmsr &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); in mii_set_link()
42 mii->anlpar = MII_ANAR_TX; in mii_set_link()
48 mii->bmcr = MII_BMCR_FD | MII_BMCR_AUTOEN | MII_BMCR_SPEED; in mii_reset()
49 mii->bmsr = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD | in mii_reset()
51 mii->anar = MII_ANAR_TXFD | MII_ANAR_TX | MII_ANAR_10FD | MII_ANAR_10 | in mii_reset()
53 mii->anlpar = MII_ANAR_TX; in mii_reset()
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H A Dstellaris_enet.c12 #include "hw/qdev-properties.h"
76 /* Real hardware has a 2k fifo, which works out to be at most 31 packets.
77 We implement a full 31 packet fifo. */
104 * np is a size; hence their valid upper bounds differ. in stellaris_enet_post_load()
106 if (s->next_packet >= ARRAY_SIZE(s->rx)) { in stellaris_enet_post_load()
107 return -1; in stellaris_enet_post_load()
110 if (s->np > ARRAY_SIZE(s->rx)) { in stellaris_enet_post_load()
111 return -1; in stellaris_enet_post_load()
114 for (i = 0; i < ARRAY_SIZE(s->rx); i++) { in stellaris_enet_post_load()
115 if (s->rx[i].len > ARRAY_SIZE(s->rx[i].data)) { in stellaris_enet_post_load()
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/openbmc/openpower-sbe-interface/
H A Dsbe_chipOp_handler.hpp21 * @brief Helper function for invokeSBEChipOperation(),to write to the SBE FIFO
26 * - Device driver internal failures
28 * @param[in] FIFO device path associated with SBE.
29 * @param[in] Command buffer to be written to the SBE FIFO
47 * - SBE Internal failures
49 * @param[in/out] On input - SBE data obtained from the SBE FIFO device.
50 * On output - Chip operation data after removing the response
59 * write to the SBE FIFO and validates the data obtained by the SBE. It throws
63 * - Device driver failures
64 * - SBE internal failures
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/openbmc/qemu/include/qemu/
H A Dfifo32.h4 * Copyright (c) 2016 Jean-Christophe Dubois
21 Fifo8 fifo; member
26 * @fifo: struct Fifo32 to initialise with new FIFO
27 * @capacity: capacity of the newly created FIFO expressed in 32 bit words
29 * Create a FIFO of the specified size. Clients should call fifo32_destroy()
30 * when finished using the fifo. The FIFO is initially empty.
33 static inline void fifo32_create(Fifo32 *fifo, uint32_t capacity) in fifo32_create() argument
35 fifo8_create(&fifo->fifo, capacity * sizeof(uint32_t)); in fifo32_create()
40 * @fifo: FIFO to cleanup
42 * Cleanup a FIFO created with fifo32_create(). Frees memory created for FIFO
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/openbmc/u-boot/drivers/usb/musb/
H A Dmusb_core.c1 // SPDX-License-Identifier: GPL-2.0+
8 * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
27 writew(0, &musbr->intrtxe); in musb_start()
28 writew(0, &musbr->intrrxe); in musb_start()
29 writeb(0, &musbr->intrusbe); in musb_start()
30 writeb(0, &musbr->testmode); in musb_start()
33 writeb(MUSB_POWER_HSENAB, &musbr->power); in musb_start()
41 devctl = readb(&musbr->devctl); in musb_start()
42 writeb(devctl | MUSB_DEVCTL_SESSION, &musbr->devctl); in musb_start()
51 writeb(idx, &musbr->dir##fifosz); \
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/openbmc/u-boot/doc/device-tree-bindings/spi/
H A Dspi-cadence.txt2 --------------------------------------------
5 - compatible : should be "cdns,qspi-nor"
6 - reg : 1.Physical base address and size of SPI registers map.
7 2. Physical base address & size of NOR Flash.
8 - clocks : Clock phandles (see clock bindings for details).
9 - cdns,fifo-depth : Size of the data FIFO in words.
10 - cdns,fifo-width : Bus width of the data FIFO in bytes.
11 - cdns,trigger-address : 32-bit indirect AHB trigger address.
12 - cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
13 - status : enable in requried dts.
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/openbmc/u-boot/doc/device-tree-bindings/net/
H A Daltera_tse.txt1 * Altera Triple-Speed Ethernet MAC driver (TSE)
4 - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
5 be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
6 - reg: Address and length of the register set for the device. It contains
7 the information of registers in the same order as described by reg-names
8 - reg-names: Should contain the reg names
16 - interrupts: Should contain the TSE interrupts and it's mode.
17 - interrupt-names: Should contain the interrupt names
20 - rx-fifo-depth: MAC receive FIFO buffer depth in bytes
21 - tx-fifo-depth: MAC transmit FIFO buffer depth in bytes
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/openbmc/u-boot/arch/arm/include/asm/arch-armada100/
H A Dspi.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Written-by: Ajay Bhargav <contact@8051projects.net>
24 u32 sscr0; /* SSP Control Register 0 - 0x000 */
25 u32 sscr1; /* SSP Control Register 1 - 0x004 */
26 u32 sssr; /* SSP Status Register - 0x008 */
27 u32 ssitr; /* SSP Interrupt Test Register - 0x00C */
28 u32 ssdr; /* SSP Data Register - 0x010 */
30 u32 ssto; /* SSP Timeout Register - 0x028 */
31 u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */
32 u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */
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/openbmc/qemu/hw/dma/
H A Dsoc_dma.c2 * On-chip DMA controller framework.
21 #include "qemu/error-report.h"
27 memcpy(ch->paddr[0], ch->paddr[1], ch->bytes); in transfer_mem2mem()
28 ch->paddr[0] += ch->bytes; in transfer_mem2mem()
29 ch->paddr[1] += ch->bytes; in transfer_mem2mem()
34 ch->io_fn[1](ch->io_opaque[1], ch->paddr[0], ch->bytes); in transfer_mem2fifo()
35 ch->paddr[0] += ch->bytes; in transfer_mem2fifo()
40 ch->io_fn[0](ch->io_opaque[0], ch->paddr[1], ch->bytes); in transfer_fifo2mem()
41 ch->paddr[1] += ch->bytes; in transfer_fifo2mem()
51 if (ch->bytes > fifo_size) in transfer_fifo2fifo()
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/openbmc/qemu/semihosting/
H A Dconsole.c12 * re-directed to gdb (if currently being used to debug) or even
13 * re-directed elsewhere.
15 * SPDX-License-Identifier: GPL-2.0-or-later
21 #include "exec/cpu-common.h"
25 #include "chardev/char-fe.h"
26 #include "qemu/main-loop.h"
37 Fifo8 fifo; member
48 return (int)fifo8_num_free(&c->fifo); in console_can_read()
55 cs->halted = 0; in console_wake_up()
59 static void console_read(void *opaque, const uint8_t *buf, int size) in console_read() argument
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/openbmc/qemu/hw/char/
H A Dtrace-events12 # virtio-serial-bus.c
18 # virtio-console.c
20 virtio_console_chr_read(unsigned int port, int size) "port %u, size %d"
24 …_tty_read(void *dev, unsigned int addr, unsigned int size, uint64_t value) "tty: %p reg: 0x%02x si…
25 …tty_write(void *dev, unsigned int addr, unsigned int size, uint64_t value) "tty: %p reg: 0x%02x si…
27 goldfish_tty_receive(void *dev, unsigned int size) "tty: %p size: %u"
56 imx_serial_read(const char *chrname, uint64_t addr, uint64_t value) "%s:[0x%03" PRIu64 "] -> 0x%08"…
57 imx_serial_write(const char *chrname, uint64_t addr, uint64_t value) "%s:[0x%03" PRIu64 "] <- 0x%08…
63 pl011_read_fifo(unsigned rx_fifo_used, size_t rx_fifo_depth) "RX FIFO read, used %u/%zu"
65 …o_used, size_t rx_fifo_depth, unsigned rx_fifo_available) "LCR 0x%02x, RX FIFO used %u/%zu, can_re…
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/openbmc/u-boot/drivers/sound/
H A Dbroadwell_i2s.h1 /* SPDX-License-Identifier: GPL-2.0+ */
45 u32 reserved0[29]; /* 0x14 - 0x77 */
57 u32 reserved0[5]; /* 0x14 - 0x27 */
141 /* Transmit FIFO Underrun */
145 /* Receiver Time-out Interrupt */
149 /* Received FIFO Level */
152 /* Transmit FIFO Level */
155 /* Receive FIFO Overrun */
157 /* Receive FIFO Service Request */
159 /* Transmit FIFO Service Request */
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/openbmc/u-boot/drivers/qe/
H A Duccf.h1 /* SPDX-License-Identifier: GPL-2.0+ */
65 #define UCC_GETH_URFS_INIT 512 /* Rx virtual FIFO size */
68 #define UCC_GETH_UTFS_INIT 512 /* Tx virtual FIFO size */
74 #define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ /* Rx virtual FIFO size */
77 #define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/ /* Tx virtual FIFO size */
/openbmc/qemu/hw/ssi/
H A Dtrace-events3 aspeed_smc_flash_set_segment(int cs, uint64_t reg, uint64_t start, uint64_t end) "CS%d segreg=0x%"PRIx64" [ 0x%"PRIx64" - 0x%"PRIx64" ]"
4 aspeed_smc_flash_read(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d"
6 aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d"
7 aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
9 aspeed_smc_dma_rw(const char *dir, uint32_t flash_addr, uint64_t dram_addr, uint32_t size) "%s flash:@0x%08x dram:@0x%" PRIx64 " size:0x%08x"
10 aspeed_smc_write(uint64_t addr, uint32_t size, uint64_
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/openbmc/qemu/hw/block/
H A Dfdc.c33 #include "qemu/error-report.h"
38 #include "hw/qdev-properties.h"
39 #include "hw/qdev-properties-system.h"
42 #include "system/block-backend.h"
46 #include "qemu/main-loop.h"
50 #include "fdc-internal.h"
74 #define TYPE_FLOPPY_BUS "floppy-bus"
88 bus->fdc = fdc; in floppy_bus_create()
95 /* In many cases, the total sector size of a format is enough to uniquely
97 * formats of different physical size, and these are noted below by
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/openbmc/qemu/hw/misc/
H A Dmips_itu.c2 * Inter-Thread Communication Unit emulation.
27 #include "hw/qdev-properties.h"
73 return &itu->tag_io; in mips_itu_get_tag_region()
76 static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size) in itc_tag_read() argument
86 return tag->ITCAddressMap[index]; in itc_tag_read()
91 uint64_t *am = &tag->ITCAddressMap[0]; in itc_reconfigure()
92 MemoryRegion *mr = &tag->storage_io; in itc_reconfigure()
94 uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK); in itc_reconfigure() local
98 if (!(size & (size - 1))) { in itc_reconfigure()
99 memory_region_set_size(mr, size); in itc_reconfigure()
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/openbmc/u-boot/arch/arm/dts/
H A Dstv0991.dts1 /dts-v1/;
6 #address-cells = <1>;
7 #size-cells = <1>;
10 stdout-path = &uart0;
29 compatible = "cdns,qspi-nor";
30 #address-cells = <1>;
31 #size-cells = <0>;
35 cdns,fifo-depth = <256>;
36 cdns,fifo-width = <4>;
37 cdns,trigger-address = <0x40000000>;
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/openbmc/qemu/include/hw/i2c/
H A Dnpcm7xx_smbus.h30 /* Size of the FIFO buffer. */
43 * struct NPCM7xxSMBusState - System Management Bus device state.
59 * @fif_ctl: The FIFO control register.
60 * @fif_cts: The FIFO control status register.
62 * @txf_ctl: The transmit FIFO control register.
64 * @txf_sts: The transmit FIFO status register.
65 * @rxf_sts: The receive FIFO status register.
66 * @rxf_ctl: The receive FIFO control register.
67 * @rx_fifo: The FIFO buffer for receiving in FIFO mode.
109 #define TYPE_NPCM7XX_SMBUS "npcm7xx-smbus"
/openbmc/qemu/hw/scsi/
H A Desp.c4 * Copyright (c) 2005-2006 Fabrice Bellard
6 * Copyright (c) 2023 Mark Cave-Ayland
39 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
41 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
48 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { in esp_raise_irq()
49 s->rregs[ESP_RSTAT] |= STAT_INT; in esp_raise_irq()
50 qemu_irq_raise(s->irq); in esp_raise_irq()
57 if (s->rregs[ESP_RSTAT] & STAT_INT) { in esp_lower_irq()
58 s->rregs[ESP_RSTAT] &= ~STAT_INT; in esp_lower_irq()
59 qemu_irq_lower(s->irq); in esp_lower_irq()
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/openbmc/qemu/hw/vmapple/
H A Daes.c7 * See the COPYING file in the top-level directory.
9 * SPDX-License-Identifier: GPL-2.0-or-later
38 #define CMD_KEY_KEY_LEN_MASK ((CMD_KEY_KEY_LEN_NUM - 1u) << CMD_KEY_KEY_LEN_SHIFT)
130 uint32_t fifo[MAX_FIFO_SIZE]; member
140 qemu_set_irq(s->irq, !!(s->irq_status & s->irq_enable)); in aes_update_irq()
143 static uint64_t aes1_read(void *opaque, hwaddr offset, unsigned size) in aes1_read() argument
150 res = s->status; in aes1_read()
153 res = s->irq_status; in aes1_read()
156 res = s->irq_enable; in aes1_read()
159 res = s->watermark; in aes1_read()
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/openbmc/u-boot/drivers/spi/
H A Dzynq_qspi.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
22 #define ZYNQ_QSPI_CR_FW_MASK GENMASK(7, 6) /* FIFO width */
35 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
36 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
37 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
38 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
40 #define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/
41 #define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */
101 struct zynq_qspi_platdata *plat = bus->platdata; in zynq_qspi_ofdata_to_platdata()
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/openbmc/u-boot/drivers/serial/
H A Dserial_pic32.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <dt-bindings/clock/microchip,clock.h>
52 /* wait for TX FIFO to empty */ in pic32_serial_init()
64 writel(div - 1, base + U_BRG); in pic32_serial_init()
74 /* Check whether any char pending in RX fifo */
86 * chars in rx-fifo. Only it can be known whether there is any. in pic32_uart_pending_input()
96 return pic32_uart_pending_input(priv->base); in pic32_uart_pending()
98 return !(readl(priv->base + U_STA) & UART_TX_EMPTY); in pic32_uart_pending()
105 return pic32_serial_init(priv->base, priv->uartclk, baudrate); in pic32_uart_setbrg()
112 /* Check if Tx FIFO is full */ in pic32_uart_putc()
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