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/openbmc/linux/lib/
H A Dkfifo.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * A generic kernel FIFO implementation
17 * internal helper to calculate the unused elements in a fifo
19 static inline unsigned int kfifo_unused(struct __kfifo *fifo) in kfifo_unused() argument
21 return (fifo->mask + 1) - (fifo->in - fifo->out); in kfifo_unused()
24 int __kfifo_alloc(struct __kfifo *fifo, unsigned int size, in __kfifo_alloc() argument
31 size = roundup_pow_of_two(size); in __kfifo_alloc()
33 fifo->in = 0; in __kfifo_alloc()
34 fifo->out = 0; in __kfifo_alloc()
35 fifo->esize = esize; in __kfifo_alloc()
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/openbmc/linux/include/linux/
H A Dkfifo.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * A generic kernel FIFO implementation
12 * How to porting drivers to the new generic FIFO API:
14 * - Modify the declaration of the "struct kfifo *" object into a
15 * in-place "struct kfifo" object
16 * - Init the in-place object with kfifo_alloc() or kfifo_init()
17 * Note: The address of the in-place "struct kfifo" object must be
19 * - Replace the use of __kfifo_put into kfifo_in and __kfifo_get
21 * - Replace the use of kfifo_put into kfifo_in_spinlocked and kfifo_get
26 * - The formerly __kfifo_* functions are renamed into kfifo_*
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H A Dpxa2xx_ssp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * This driver supports the following PXA CPU/SSP ports:-
49 #define SSCR0_DSS GENMASK(3, 0) /* Data Size Select (mask) */
50 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
60 #define SSCR0_EDSS BIT(20) /* Extended data size select */
62 #define SSCR0_RIM BIT(22) /* Receive FIFO overrun interrupt mask */
63 #define SSCR0_TUM BIT(23) /* Transmit FIFO underrun interrupt mask */
65 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
66 #define SSCR0_FPCKE BIT(29) /* FIFO packing enable */
70 #define SSCR1_RIE BIT(0) /* Receive FIFO Interrupt Enable */
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/openbmc/linux/drivers/platform/mellanox/
H A Dmlxbf-tmfifo.c1 // SPDX-License-Identifier: GPL-2.0+
24 #include "mlxbf-tmfifo-regs.h"
26 /* Vring size. */
29 /* Console Tx buffer size. */
35 /* House-keeping timer interval. */
38 /* Virtual devices sharing the TM FIFO. */
53 /* ACPI UID for BlueField-3. */
59 * struct mlxbf_tmfifo_vring - Structure of the TmFifo virtual ring
71 * @num: vring size (number of descriptors)
72 * @align: vring alignment size
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/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpc5121-psc.txt4 ----------------
7 are specified by fsl,mpc5121-psc-uart nodes in the
8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is required there:
11 fsl,mpc512x-psc-uart nodes
12 --------------------------
15 - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
17 - reg : Offset and length of the register set for the PSC device
18 - interrupts : <a b> where a is the interrupt number of the
19 PSC FIFO Controller and b is a field that represents an
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/openbmc/linux/drivers/md/bcache/
H A Dutil.h1 /* SPDX-License-Identifier: GPL-2.0 */
36 size_t size, used; \
43 (heap)->used = 0; \
44 (heap)->size = (_size); \
45 _bytes = (heap)->size * sizeof(*(heap)->data); \
46 (heap)->data = kvmalloc(_bytes, (gfp) & GFP_KERNEL); \
47 (heap)->data; \
52 kvfree((heap)->data); \
53 (heap)->data = NULL; \
56 #define heap_swap(h, i, j) swap((h)->data[i], (h)->data[j])
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/openbmc/linux/sound/soc/meson/
H A Daiu-fifo.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/dma-mapping.h>
11 #include <sound/soc-dai.h>
13 #include "aiu-fifo.h"
28 struct snd_soc_pcm_runtime *rtd = ss->private_data; in aiu_fifo_dai()
37 struct aiu_fifo *fifo = snd_soc_dai_dma_data_get_playback(dai); in aiu_fifo_pointer() local
38 struct snd_pcm_runtime *runtime = substream->runtime; in aiu_fifo_pointer()
41 addr = snd_soc_component_read(component, fifo->mem_offset + AIU_MEM_RD); in aiu_fifo_pointer()
43 return bytes_to_frames(runtime, addr - (unsigned int)runtime->dma_addr); in aiu_fifo_pointer()
48 struct snd_soc_component *component = dai->component; in aiu_fifo_enable()
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H A Daxg-fifo.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
15 #include <sound/soc-dai.h>
17 #include "axg-fifo.h"
21 * capture frontend DAI. The logic behind this two types of fifo is very
49 struct snd_soc_pcm_runtime *rtd = ss->private_data; in axg_fifo_dai()
65 return dai->dev; in axg_fifo_dev()
68 static void __dma_enable(struct axg_fifo *fifo, bool enable) in __dma_enable() argument
70 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_DMA_EN, in __dma_enable()
77 struct axg_fifo *fifo = axg_fifo_data(ss); in axg_fifo_pcm_trigger() local
83 __dma_enable(fifo, true); in axg_fifo_pcm_trigger()
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dibm,emac.txt8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
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/openbmc/linux/drivers/net/ethernet/intel/fm10k/
H A Dfm10k_mbx.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2019 Intel Corporation. */
7 * fm10k_fifo_init - Initialize a message FIFO
8 * @fifo: pointer to FIFO
9 * @buffer: pointer to memory to be used to store FIFO
10 * @size: maximum message size to store in FIFO, must be 2^n - 1
12 static void fm10k_fifo_init(struct fm10k_mbx_fifo *fifo, u32 *buffer, u16 size) in fm10k_fifo_init() argument
14 fifo->buffer = buffer; in fm10k_fifo_init()
15 fifo->size = size; in fm10k_fifo_init()
16 fifo->head = 0; in fm10k_fifo_init()
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/openbmc/linux/arch/powerpc/boot/dts/
H A Dmpc5121.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2007-2008 Freescale Semiconductor Inc.
8 #include <dt-bindings/clock/mpc512x-clock.h>
10 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&ipic>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <0x20>; /* 32 bytes */
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H A Deiger.dts11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
40 d-cache-line-size = <32>;
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/openbmc/qemu/hw/audio/
H A Dtrace-events6 cs4231_mem_writel_reg(uint32_t reg, uint32_t old, uint32_t val) "write reg %d: 0x%08x -> 0x%08x"
7 cs4231_mem_writel_dreg(uint32_t reg, uint32_t old, uint32_t val) "write dreg %d: 0x%02x -> 0x%02x"
12 es1370_frame_count_rd(int ch, uint32_t curr, uint32_t size) "ch=%d CURR_CT=%u BUF_SIZE=%u"
13 es1370_frame_count_wr(int ch, uint32_t curr, uint32_t size) "ch=%d CURR_CT=%u BUF_SIZE=%u"
20 # hda-codec.c
26 #via-ac97.c
27 via_ac97_codec_write(uint8_t addr, uint16_t val) "0x%x <- 0x%x"
29 via_ac97_sgd_read(uint64_t addr, unsigned size, uint64_t val) "0x%"PRIx64" %d -> 0x%"PRIx64
30 via_ac97_sgd_write(uint64_t addr, unsigned size, uint64_t val) "0x%"PRIx64" %d <- 0x%"PRIx64
33 asc_read_fifo(const char fifo, int reg, unsigned size, uint64_t value) "fifo %c reg=0x%03x size=%u …
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H A Dasc.c7 * Copyright (c) 2012-2018 Laurent Vivier <laurent@vivier.eu>
8 * Copyright (c) 2022 Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
10 * SPDX-License-Identifier: GPL-2.0-or-later
19 #include "hw/qdev-properties.h"
36 * 1=FIFO mode,
42 * 0x803: FIFO MODE
43 * bit 7=clear FIFO,
44 * bit 1="non-ROM companding",
46 * 0x804: FIFO IRQ STATUS
52 * bits 0-3 wavetables 0-3 start
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/openbmc/qemu/hw/net/
H A Dallwinner_emac.c7 * This model is based on reverse-engineering of Linux kernel driver.
27 #include "hw/qdev-properties.h"
37 mii->bmsr |= MII_BMSR_LINK_ST | MII_BMSR_AN_COMP; in mii_set_link()
38 mii->anlpar |= MII_ANAR_TXFD | MII_ANAR_10FD | MII_ANAR_10 | in mii_set_link()
41 mii->bmsr &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); in mii_set_link()
42 mii->anlpar = MII_ANAR_TX; in mii_set_link()
48 mii->bmcr = MII_BMCR_FD | MII_BMCR_AUTOEN | MII_BMCR_SPEED; in mii_reset()
49 mii->bmsr = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD | in mii_reset()
51 mii->anar = MII_ANAR_TXFD | MII_ANAR_TX | MII_ANAR_10FD | MII_ANAR_10 | in mii_reset()
53 mii->anlpar = MII_ANAR_TX; in mii_reset()
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/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Dmac.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
94 return -ETIMEDOUT; in rtw_mac_pre_system_cfg()
107 return -EINVAL; in rtw_mac_pre_system_cfg()
156 if (cmd->base == RTW_PWR_ADDR_SDIO) in rtw_pwr_cmd_polling()
157 offset = cmd->offset | SDIO_LOCAL_OFFSET; in rtw_pwr_cmd_polling()
159 offset = cmd->offset; in rtw_pwr_cmd_polling()
161 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value)) in rtw_pwr_cmd_polling()
169 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D) in rtw_pwr_cmd_polling()
173 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D) in rtw_pwr_cmd_polling()
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/openbmc/linux/samples/kfifo/
H A Ddma-example.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Sample fifo dma implementation
13 * This module shows how to handle fifo dma operations.
16 /* fifo size in elements (bytes) */
19 static struct kfifo fifo; variable
28 printk(KERN_INFO "DMA fifo test start\n"); in example_init()
30 if (kfifo_alloc(&fifo, FIFO_SIZE, GFP_KERNEL)) { in example_init()
32 return -ENOMEM; in example_init()
35 printk(KERN_INFO "queue size: %u\n", kfifo_size(&fifo)); in example_init()
37 kfifo_in(&fifo, "test", 4); in example_init()
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dnv50.c38 nvkm_ramht_remove(chan->ramht, hash); in nv50_eobj_ramht_del()
44 return nvkm_ramht_insert(chan->ramht, eobj, 0, 4, eobj->handle, engn->id << 20); in nv50_eobj_ramht_add()
50 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in nv50_chan_stop()
52 nvkm_mask(device, 0x002600 + (chan->id * 4), 0x80000000, 0x00000000); in nv50_chan_stop()
58 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in nv50_chan_start()
60 nvkm_mask(device, 0x002600 + (chan->id * 4), 0x80000000, 0x80000000); in nv50_chan_start()
66 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in nv50_chan_unbind()
68 nvkm_wr32(device, 0x002600 + (chan->id * 4), 0x00000000); in nv50_chan_unbind()
74 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in nv50_chan_bind()
76 nvkm_wr32(device, 0x002600 + (chan->id * 4), chan->ramfc->addr >> 12); in nv50_chan_bind()
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/openbmc/linux/drivers/gpu/drm/msm/
H A Dmsm_rd.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * tail -f /sys/kernel/debug/dri/<minor>/rd > logfile.rd
18 * tail -f /sys/kernel/debug/dri/<minor>/hangrd > logfile.rd
26 * The module-param "rd_full", which defaults to false, enables snapshotting
27 * all (non-written) buffers in the submit, rather than just cmdstream bo's.
54 RD_GPUADDR, /* u32 gpuaddr, u32 size */
72 (CIRC_CNT((circ)->head, (circ)->tail, BUF_SZ))
74 (CIRC_CNT_TO_END((circ)->head, (circ)->tail, BUF_SZ))
77 (CIRC_SPACE((circ)->head, (circ)->tail, BUF_SZ))
79 (CIRC_SPACE_TO_END((circ)->head, (circ)->tail, BUF_SZ))
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/openbmc/openpower-sbe-interface/
H A Dsbe_chipOp_handler.hpp21 * @brief Helper function for invokeSBEChipOperation(),to write to the SBE FIFO
26 * - Device driver internal failures
28 * @param[in] FIFO device path associated with SBE.
29 * @param[in] Command buffer to be written to the SBE FIFO
47 * - SBE Internal failures
49 * @param[in/out] On input - SBE data obtained from the SBE FIFO device.
50 * On output - Chip operation data after removing the response
59 * write to the SBE FIFO and validates the data obtained by the SBE. It throws
63 * - Device driver failures
64 * - SBE internal failures
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/openbmc/u-boot/drivers/usb/musb/
H A Dmusb_core.c1 // SPDX-License-Identifier: GPL-2.0+
8 * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
27 writew(0, &musbr->intrtxe); in musb_start()
28 writew(0, &musbr->intrrxe); in musb_start()
29 writeb(0, &musbr->intrusbe); in musb_start()
30 writeb(0, &musbr->testmode); in musb_start()
33 writeb(MUSB_POWER_HSENAB, &musbr->power); in musb_start()
41 devctl = readb(&musbr->devctl); in musb_start()
42 writeb(devctl | MUSB_DEVCTL_SESSION, &musbr->devctl); in musb_start()
51 writeb(idx, &musbr->dir##fifosz); \
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/openbmc/qemu/include/qemu/
H A Dfifo32.h4 * Copyright (c) 2016 Jean-Christophe Dubois
21 Fifo8 fifo; member
26 * @fifo: struct Fifo32 to initialise with new FIFO
27 * @capacity: capacity of the newly created FIFO expressed in 32 bit words
29 * Create a FIFO of the specified size. Clients should call fifo32_destroy()
30 * when finished using the fifo. The FIFO is initially empty.
33 static inline void fifo32_create(Fifo32 *fifo, uint32_t capacity) in fifo32_create() argument
35 fifo8_create(&fifo->fifo, capacity * sizeof(uint32_t)); in fifo32_create()
40 * @fifo: FIFO to cleanup
42 * Cleanup a FIFO created with fifo32_create(). Frees memory created for FIFO
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/openbmc/linux/drivers/char/xilinx_hwicap/
H A Dfifo_icap.c24 * (c) Copyright 2007-2008 Xilinx Inc.
39 #define XHI_WF_OFFSET 0x100 /* Write FIFO */
40 #define XHI_RF_OFFSET 0x104 /* Read FIFO */
41 #define XHI_SZ_OFFSET 0x108 /* Size Register */
44 #define XHI_WFV_OFFSET 0x114 /* Write FIFO Vacancy Register */
45 #define XHI_RFO_OFFSET 0x118 /* Read FIFO Occupancy Register */
66 #define XHI_IPIXR_RFULL_MASK 0x00000008 /* Read FIFO Full */
67 #define XHI_IPIXR_WEMPTY_MASK 0x00000004 /* Write FIFO Empty */
68 #define XHI_IPIXR_RDP_MASK 0x00000002 /* Read FIFO half full */
69 #define XHI_IPIXR_WRP_MASK 0x00000001 /* Write FIFO half full */
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/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dampdu.c31 /* max Tx ba window size (in pdu) */
33 /* default Tx ba window size (in pdu) */
35 /* default Rx ba window size (in pdu) */
37 /* max Rx ba window size (in pdu) */
52 #define NUM_FFPLD_FIFO 4 /* number of fifo concerned by pre-loading */
56 #define FFPLD_MPDU_SIZE 1800 /* estimate of maximum mpdu size */
76 #define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
77 #define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
79 /* structure to hold tx fifo information and pre-loading state
85 * ampdu_pld_size: number of bytes to be pre-loaded
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/openbmc/linux/tools/testing/selftests/tc-testing/tc-tests/qdiscs/
H A Dfifo.json5 …"__comment": "When omitted, queue size in bfifo is calculated as: txqueuelen * (MTU + LinkLayerHdr…
8 "fifo"
16 "matchPattern": "qdisc bfifo 1: root.*limit [0-9]+b",
26 …"__comment": "When omitted, queue size in pfifo is defaulted to the interface's txqueuelen value.",
29 "fifo"
37 "matchPattern": "qdisc pfifo 1: root.*limit [0-9]+p",
49 "fifo"
57 "matchPattern": "qdisc bfifo ffff: root.*limit [0-9]+b",
66 "name": "Add bfifo qdisc on egress with queue size of 3000 bytes",
69 "fifo"
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