7  * This model is based on reverse-engineering of Linux kernel driver.
27 #include "hw/qdev-properties.h"
37         mii->bmsr |= MII_BMSR_LINK_ST | MII_BMSR_AN_COMP;  in mii_set_link()
38         mii->anlpar |= MII_ANAR_TXFD | MII_ANAR_10FD | MII_ANAR_10 |  in mii_set_link()
41         mii->bmsr &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP);  in mii_set_link()
42         mii->anlpar = MII_ANAR_TX;  in mii_set_link()
48     mii->bmcr = MII_BMCR_FD | MII_BMCR_AUTOEN | MII_BMCR_SPEED;  in mii_reset()
49     mii->bmsr = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD |  in mii_reset()
51     mii->anar = MII_ANAR_TXFD | MII_ANAR_TX | MII_ANAR_10FD | MII_ANAR_10 |  in mii_reset()
53     mii->anlpar = MII_ANAR_TX;  in mii_reset()
60     RTL8201CPState *mii = &s->mii;  in RTL8201CP_mdio_read()
63     if (addr == s->phy_addr) {  in RTL8201CP_mdio_read()
66             return mii->bmcr;  in RTL8201CP_mdio_read()
68             return mii->bmsr;  in RTL8201CP_mdio_read()
74             return mii->anar;  in RTL8201CP_mdio_read()
76             return mii->anlpar;  in RTL8201CP_mdio_read()
100     RTL8201CPState *mii = &s->mii;  in RTL8201CP_mdio_write()
103     if (addr == s->phy_addr) {  in RTL8201CP_mdio_write()
107                 nc = qemu_get_queue(s->nic);  in RTL8201CP_mdio_write()
108                 mii_reset(mii, !nc->link_down);  in RTL8201CP_mdio_write()
110                 mii->bmcr = value;  in RTL8201CP_mdio_write()
114             mii->anar = value;  in RTL8201CP_mdio_write()
122                           "allwinner_emac: write to read-only mii reg 0x%x\n",  in RTL8201CP_mdio_write()
144     qemu_set_irq(s->irq, (s->int_sta & s->int_ctl) != 0);  in aw_emac_update_irq()
149     fifo8_reset(&s->tx_fifo[chan]);  in aw_emac_tx_reset()
150     s->tx_length[chan] = 0;  in aw_emac_tx_reset()
155     fifo8_reset(&s->rx_fifo);  in aw_emac_rx_reset()
156     s->rx_num_packets = 0;  in aw_emac_rx_reset()
157     s->rx_packet_size = 0;  in aw_emac_rx_reset()
158     s->rx_packet_pos = 0;  in aw_emac_rx_reset()
161 static void fifo8_push_word(Fifo8 *fifo, uint32_t val)  in fifo8_push_word()  argument
163     fifo8_push(fifo, val);  in fifo8_push_word()
164     fifo8_push(fifo, val >> 8);  in fifo8_push_word()
165     fifo8_push(fifo, val >> 16);  in fifo8_push_word()
166     fifo8_push(fifo, val >> 24);  in fifo8_push_word()
169 static uint32_t fifo8_pop_word(Fifo8 *fifo)  in fifo8_pop_word()  argument
173     ret = fifo8_pop(fifo);  in fifo8_pop_word()
174     ret |= fifo8_pop(fifo) << 8;  in fifo8_pop_word()
175     ret |= fifo8_pop(fifo) << 16;  in fifo8_pop_word()
176     ret |= fifo8_pop(fifo) << 24;  in fifo8_pop_word()
189     return (s->ctl & EMAC_CTL_RX_EN) && (fifo8_num_free(&s->rx_fifo) >= 1532);  in aw_emac_can_receive()
193                                size_t size)  in aw_emac_receive()  argument
196     Fifo8 *fifo = &s->rx_fifo;  in aw_emac_receive()  local
200     padded_size = size > 60 ? size : 60;  in aw_emac_receive()
203     if (!(s->ctl & EMAC_CTL_RX_EN) || (fifo8_num_free(fifo) < total_size)) {  in aw_emac_receive()
204         return -1;  in aw_emac_receive()
207     fifo8_push_word(fifo, EMAC_UNDOCUMENTED_MAGIC);  in aw_emac_receive()
208     fifo8_push_word(fifo, EMAC_RX_HEADER(padded_size + CRC_SIZE,  in aw_emac_receive()
210     fifo8_push_all(fifo, buf, size);  in aw_emac_receive()
211     crc = crc32(~0, buf, size);  in aw_emac_receive()
213     if (padded_size != size) {  in aw_emac_receive()
214         fifo8_push_all(fifo, padding, padded_size - size);  in aw_emac_receive()
215         crc = crc32(crc, padding, padded_size - size);  in aw_emac_receive()
218     fifo8_push_word(fifo, crc);  in aw_emac_receive()
219     fifo8_push_all(fifo, padding, QEMU_ALIGN_UP(padded_size, 4) - padded_size);  in aw_emac_receive()
220     s->rx_num_packets++;  in aw_emac_receive()
222     s->int_sta |= EMAC_INT_RX;  in aw_emac_receive()
225     return size;  in aw_emac_receive()
231     NetClientState *nc = qemu_get_queue(s->nic);  in aw_emac_reset()
233     s->ctl = 0;  in aw_emac_reset()
234     s->tx_mode = 0;  in aw_emac_reset()
235     s->int_ctl = 0;  in aw_emac_reset()
236     s->int_sta = 0;  in aw_emac_reset()
237     s->tx_channel = 0;  in aw_emac_reset()
238     s->phy_target = 0;  in aw_emac_reset()
244     mii_reset(&s->mii, !nc->link_down);  in aw_emac_reset()
247 static uint64_t aw_emac_read(void *opaque, hwaddr offset, unsigned size)  in aw_emac_read()  argument
250     Fifo8 *fifo = &s->rx_fifo;  in aw_emac_read()  local
256         return s->ctl;  in aw_emac_read()
258         return s->tx_mode;  in aw_emac_read()
260         return s->tx_channel;  in aw_emac_read()
262         return s->rx_ctl;  in aw_emac_read()
264         if (!s->rx_num_packets) {  in aw_emac_read()
270         ret = fifo8_pop_word(fifo);  in aw_emac_read()
272         switch (s->rx_packet_pos) {  in aw_emac_read()
274             s->rx_packet_pos += 4;  in aw_emac_read()
277             s->rx_packet_pos += 4;  in aw_emac_read()
278             s->rx_packet_size = QEMU_ALIGN_UP(extract32(ret, 0, 16), 4);  in aw_emac_read()
281             s->rx_packet_pos += 4;  in aw_emac_read()
282             s->rx_packet_size -= 4;  in aw_emac_read()
284             if (!s->rx_packet_size) {  in aw_emac_read()
285                 s->rx_packet_pos = 0;  in aw_emac_read()
286                 s->rx_num_packets--;  in aw_emac_read()
287                 nc = qemu_get_queue(s->nic);  in aw_emac_read()
295         return s->rx_num_packets;  in aw_emac_read()
297         return s->int_ctl;  in aw_emac_read()
299         return s->int_sta;  in aw_emac_read()
302                                    extract32(s->phy_target, PHY_ADDR_SHIFT, 8),  in aw_emac_read()
303                                    extract32(s->phy_target, PHY_REG_SHIFT, 8));  in aw_emac_read()
315                           unsigned size)  in aw_emac_write()  argument
318     Fifo8 *fifo;  in aw_emac_write()  local
319     NetClientState *nc = qemu_get_queue(s->nic);  in aw_emac_write()
328         s->ctl = value;  in aw_emac_write()
334         s->tx_mode = value;  in aw_emac_write()
339         if ((value & 1) && (s->ctl & EMAC_CTL_TX_EN)) {  in aw_emac_write()
343             fifo = &s->tx_fifo[chan];  in aw_emac_write()
344             len = s->tx_length[chan];  in aw_emac_write()
346             if (len > fifo8_num_used(fifo)) {  in aw_emac_write()
347                 len = fifo8_num_used(fifo);  in aw_emac_write()
349                               "allwinner_emac: TX length > fifo data length\n");  in aw_emac_write()
352                 data = fifo8_pop_bufptr(fifo, len, &ret);  in aw_emac_write()
356                 s->int_sta |= EMAC_INT_TX_CHAN(chan);  in aw_emac_write()
362         s->tx_channel = value < NUM_TX_FIFOS ? value : 0;  in aw_emac_write()
373         s->tx_length[chan] = value;  in aw_emac_write()
376         fifo = &s->tx_fifo[s->tx_channel];  in aw_emac_write()
377         if (fifo8_num_free(fifo) < 4) {  in aw_emac_write()
379                           "allwinner_emac: TX data overruns fifo\n");  in aw_emac_write()
382         fifo8_push_word(fifo, value);  in aw_emac_write()
385         s->rx_ctl = value;  in aw_emac_write()
393         s->int_ctl = value;  in aw_emac_write()
397         s->int_sta &= ~value;  in aw_emac_write()
401         s->phy_target = value;  in aw_emac_write()
404         RTL8201CP_mdio_write(s, extract32(s->phy_target, PHY_ADDR_SHIFT, 8),  in aw_emac_write()
405                              extract32(s->phy_target, PHY_REG_SHIFT, 8), value);  in aw_emac_write()
418     mii_set_link(&s->mii, !nc->link_down);  in aw_emac_set_link()
433     .size = sizeof(NICState),
444     memory_region_init_io(&s->iomem, OBJECT(s), &aw_emac_mem_ops, s,  in aw_emac_init()
446     sysbus_init_mmio(sbd, &s->iomem);  in aw_emac_init()
447     sysbus_init_irq(sbd, &s->irq);  in aw_emac_init()
454     qemu_macaddr_default_if_unset(&s->conf.macaddr);  in aw_emac_realize()
455     s->nic = qemu_new_nic(&net_aw_emac_info, &s->conf,  in aw_emac_realize()
456                           object_get_typename(OBJECT(dev)), dev->id,  in aw_emac_realize()
457                           &dev->mem_reentrancy_guard, s);  in aw_emac_realize()
458     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);  in aw_emac_realize()
460     fifo8_create(&s->rx_fifo, RX_FIFO_SIZE);  in aw_emac_realize()
461     fifo8_create(&s->tx_fifo[0], TX_FIFO_SIZE);  in aw_emac_realize()
462     fifo8_create(&s->tx_fifo[1], TX_FIFO_SIZE);  in aw_emac_realize()
467     DEFINE_PROP_UINT8("phy-addr", AwEmacState, phy_addr, 0),
488     aw_emac_set_link(qemu_get_queue(s->nic));  in aw_emac_post_load()
522     dc->realize = aw_emac_realize;  in aw_emac_class_init()
525     dc->vmsd = &vmstate_aw_emac;  in aw_emac_class_init()