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/openbmc/u-boot/arch/arm/dts/
H A Dkirkwood-netxbig.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 * Based on netxbig_v2-setup.c,
14 #include <dt-bindings/leds/leds-netxbig.h>
16 #include "kirkwood-6281.dtsi"
21 stdout-path = &uart0;
33 #address-cells = <1>;
34 #size-cells = <1>;
35 compatible = "mxicy,mx25l4005a", "jedec,spi-nor", "spi-flash";
37 spi-max-frequency = <20000000>;
42 label = "u-boot";
[all …]
H A Dimx6sx-sdb.dtsi9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
17 compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
20 stdout-path = &uart1;
28 compatible = "pwm-backlight";
30 brightness-levels = <0 4 8 16 32 64 128 255>;
31 default-brightness-level = <6>;
34 gpio-keys {
35 compatible = "gpio-keys";
[all …]
H A Darmada-3720-uDPU.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
12 /dts-v1/;
14 #include "armada-37xx.dtsi"
15 #include "armada-3720-uDPU-u-boot.dtsi"
22 stdout-path = "serial0:115200n8";
38 #address-cells = <1>;
39 #size-cells = <0>;
40 ethphy0: ethernet-phy@0 {
43 ethphy1: ethernet-phy@1 {
[all …]
H A Duniphier-pxs3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
14 compatible = "socionext,uniphier-pxs3";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <0>;
23 cpu-map {
[all …]
H A Dstih410-b2260.dts9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
15 compatible = "st,stih410-b2260", "st,stih410";
19 linux,stdout-path = &uart1;
20 stdout-path = &uart1;
36 compatible = "gpio-leds";
40 linux,default-trigger = "heartbeat";
41 default-state = "off";
47 default-state = "off";
53 default-state = "off";
[all …]
H A Dstm32429i-eval.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015, STMicroelectronics - All Rights Reserved
7 /dts-v1/;
9 #include "stm32f429-pinctrl.dtsi"
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
14 model = "STMicroelectronics STM32429i-EVAL board";
15 compatible = "st,stm32429i-eval", "st,stm32f429";
19 stdout-path = "serial0:115200n8";
31 clk_ext_camera: clk-ext-camera {
[all …]
H A Dimx6-logicpd-baseboard.dtsi5 * This file is dual-licensed: you can use it either under the terms
46 compatible = "gpio-keys";
52 debounce-interval = <10>;
53 wakeup-source;
60 debounce-interval = <10>;
61 wakeup-source;
68 debounce-interval = <10>;
69 wakeup-source;
75 debounce-interval = <10>;
76 wakeup-source;
[all …]
H A Dam335x-draco.dts4 * Copyright (C) 2014 - Lukas Stockmann <lukas.stockmann@siemens.com>
11 /dts-v1/;
14 #include "am335x-draco.dtsi"
15 #include <dt-bindings/input/input.h>
21 /* ethernet alias is needed for the MAC address passing from U-Boot */
24 mdio-gpio0 = &mdio0;
27 gpio-keys {
28 compatible = "gpio-keys";
52 pinctrl-names = "default";
53 pinctrl-0 = <&gpio_mux_pins>;
[all …]
H A Dimx6ul-14x14-evk.dts1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
7 /dts-v1/;
13 compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
20 stdout-path = &uart1;
28 compatible = "simple-bus";
29 #address-cells = <1>;
30 #size-cells = <0>;
33 compatible = "regulator-fixed";
34 regulator-name = "VSD_3V3";
[all …]
H A Dimx6ul-pico.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
20 stdout-path = &uart6;
24 compatible = "pwm-backlight";
26 brightness-levels = <0 4 8 16 32 64 128 255>;
27 default-brightness-level = <6>;
31 reg_2p5v: regulator-2p5v {
32 compatible = "regulator-fixed";
33 regulator-name = "2P5V";
34 regulator-min-microvolt = <2500000>;
[all …]
H A Dimx6ul-9x9-evk.dts1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
7 /dts-v1/;
13 compatible = "fsl,imx6ul-9x9-evk", "fsl,imx6ul";
20 stdout-path = &uart1;
28 compatible = "simple-bus";
29 #address-cells = <1>;
30 #size-cells = <0>;
33 compatible = "regulator-fixed";
35 regulator-name = "can-3v3";
[all …]
H A Dfsl-imx8mq-evk.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
11 #include "fsl-imx8mq.dtsi"
15 compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <0>;
27 compatible = "regulator-fixed";
28 regulator-name = "VSD_3V3";
29 regulator-min-microvolt = <3300000>;
[all …]
H A Dimx6qdl-sabresd.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
16 stdout-path = &uart1;
24 compatible = "simple-bus";
25 #address-cells = <1>;
26 #size-cells = <0>;
29 compatible = "regulator-fixed";
31 regulator-name = "usb_otg_vbus";
[all …]
H A Dat91sam9g20ek_common.dtsi2 * at91sam9g20ek_common.dtsi - Device Tree file for Atmel at91sam9g20ek board
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
12 u-boot,dm-pre-reloc;
13 stdout-path = &dbgu;
22 clock-frequency = <32768>;
26 clock-frequency = <18432000>;
42 pinctrl_board_mmc0_slot1: mmc0_slot1-board {
50 u-boot,dm-pre-reloc;
55 pinctrl-0 =
70 phy-mode = "rmii";
[all …]
H A Dtegra124-nyan.dtsi1 #include <dt-bindings/input/input.h>
19 vdd-supply = <&vdd_3v3_hdmi>;
20 pll-supply = <&vdd_hdmi_pll>;
21 hdmi-supply = <&vdd_5v0_hdmi>;
23 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
24 nvidia,hpd-gpio =
36 vdd-supply = <&vdd_3v3_panel>;
52 clock-frequency = <100000>;
54 acodec: audio-codec@10 {
57 interrupt-parent = <&gpio>;
[all …]
H A Dam335x-chiliboard.dts2 * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
9 /dts-v1/;
10 #include "am335x-chilisom.dtsi"
14 compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom",
18 compatible = "gpio-leds";
19 pinctrl-names = "default";
20 pinctrl-0 = <&led_gpio_pins>;
25 default-state = "keep";
26 linux,default-trigger = "heartbeat";
32 default-state = "keep";
[all …]
H A Dam57xx-idk-common.dtsi2 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
9 #include "am57xx-industrial-grade.dtsi"
18 stdout-path = &uart3;
21 vmain: fixedregulator-vmain {
22 compatible = "regulator-fixed";
23 regulator-name = "VMAIN";
24 regulator-min-microvolt = <5000000>;
25 regulator-max-microvolt = <5000000>;
26 regulator-always-on;
27 regulator-boot-on;
[all …]
/openbmc/u-boot/drivers/net/
H A Dbcm6368-eth.c1 // SPDX-License-Identifier: GPL-2.0+
19 #define ETH_PORT_STR "brcm,enetsw-port"
120 /* PHY */
136 /* PHY */
145 static int bcm6368_mdio_read(struct bcm6368_eth_priv *priv, uint8_t ext, in bcm6368_mdio_read() argument
150 writel_be(0, priv->base + MII_SC_REG); in bcm6368_mdio_read()
156 if (ext) in bcm6368_mdio_read()
159 writel_be(val, priv->base + MII_SC_REG); in bcm6368_mdio_read()
162 return readw_be(priv->base + MII_DAT_REG); in bcm6368_mdio_read()
165 static int bcm6368_mdio_write(struct bcm6368_eth_priv *priv, uint8_t ext, in bcm6368_mdio_write() argument
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Dsdram.c1 // SPDX-License-Identifier: GPL-2.0+
21 * exported are weakly linked so that they can be over-ridden in the board
25 * For any new board with different memory devices over-ride one or more
27 * - emif_get_reg_dump()
28 * - emif_get_dmm_regs()
29 * - emif_get_device_details()
30 * - emif_get_device_timings()
280 /* Ext phy ctrl 1-35 regs */
320 /* Ext phy ctrl 1-35 regs */
360 /* Ext phy ctrl 1-35 regs */
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dddr.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
22 * Base addresses for DDR PHY cmd/data regs
43 writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg); in get_mr()
45 mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data); in get_mr()
58 writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg); in set_mr()
59 writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data); in set_mr()
83 writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl); in config_sdram_emif4d5()
84 writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw); in config_sdram_emif4d5()
85 writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); in config_sdram_emif4d5()
[all …]
/openbmc/u-boot/board/seco/mx6quq7/
H A Dmx6quq7.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Modified by: Boris Brezillon <boris.brezillon@free-electrons.com>
11 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-pins.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/boot_mode.h>
30 #include <asm/mach-imx/mxc_i2c.h>
39 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); in dram_init()
54 if (phydev->drv->config) in board_phy_config()
55 phydev->drv->config(phydev); in board_phy_config()
[all …]
/openbmc/qemu/include/hw/net/
H A Dmii.h8 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
24 /* PHY registers */
34 #define MII_CTRL1000 9 /* 1000BASE-T control */
35 #define MII_STAT1000 10 /* 1000BASE-T status */
45 /* PHY registers fields */
59 #define MII_BMSR_100TX_FD (1 << 14) /* Can do 100mbps, full-duplex */
60 #define MII_BMSR_100TX_HD (1 << 13) /* Can do 100mbps, half-duplex */
61 #define MII_BMSR_10T_FD (1 << 12) /* Can do 10mbps, full-duplex */
62 #define MII_BMSR_10T_HD (1 << 11) /* Can do 10mbps, half-duplex */
63 #define MII_BMSR_100T2_FD (1 << 10) /* Can do 100mbps T2, full-duplex */
[all …]
/openbmc/u-boot/drivers/usb/musb/
H A Dmusb_core.c1 // SPDX-License-Identifier: GPL-2.0+
8 * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
27 writew(0, &musbr->intrtxe); in musb_start()
28 writew(0, &musbr->intrrxe); in musb_start()
29 writeb(0, &musbr->intrusbe); in musb_start()
30 writeb(0, &musbr->testmode); in musb_start()
33 writeb(MUSB_POWER_HSENAB, &musbr->power); in musb_start()
35 /* Program PHY to use EXT VBUS if required */ in musb_start()
41 devctl = readb(&musbr->devctl); in musb_start()
42 writeb(devctl | MUSB_DEVCTL_SESSION, &musbr->devctl); in musb_start()
[all …]
/openbmc/qemu/pc-bios/dtb/
H A Dpetalogix-ml605.dts5 * SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
11 #address-cells = < 0x01 >;
12 #size-cells = < 0x01 >;
22 ethernet0 = "/axi/axi-ethernet@82780000";
28 stdout-path = "/axi/serial@83e00000";
32 #address-cells = < 0x01 >;
34 #size-cells = < 0x00 >;
37 clock-frequency = < 0xbebc200 >;
38 compatible = "xlnx,microblaze-8.10.a";
[all …]
/openbmc/qemu/hw/net/
H A De1000_regs.h4 Copyright(c) 1999 - 2006 Intel Corporation.
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
37 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
38 #define E1000_EIAC 0x000DC /* Ext. Interrupt Auto Clear - RW */
39 #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */
40 #define E1000_EITR 0x000E8 /* Extended Interrupt Throttling Rate - RW */
41 #define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
42 #define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
43 #define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
[all …]

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