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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dingenic,cgu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
16 - Paul Cercueil <paul@crapouillou.net>
23 - ingenic,jz4740-cgu
24 - ingenic,jz4725b-cgu
25 - ingenic,jz4755-cgu
26 - ingenic,jz4760-cgu
27 - ingenic,jz4760b-cgu
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dcpsw-phy-sel.txt1 TI CPSW Phy mode Selection Device Tree Bindings (DEPRECATED)
2 -----------------------------------------------
5 - compatible : Should be "ti,am3352-cpsw-phy-sel" for am335x platform and
6 "ti,dra7xx-cpsw-phy-sel" for dra7xx platform
7 "ti,am43xx-cpsw-phy-sel" for am43xx platform
8 - reg : physical base address and size of the cpsw
10 - reg-names : names of the register map given in "reg" node
13 -rmii-clock-ext : If present, the driver will configure the RMII
18 phy_sel: cpsw-phy-sel@44e10650 {
19 compatible = "ti,am3352-cpsw-phy-sel";
[all …]
/openbmc/linux/drivers/net/phy/
H A Dsfp.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/mdio/mdio-i2c.h>
13 #include <linux/phy.h>
150 "mod-def0",
152 "tx-fault",
153 "tx-disable",
154 "rate-select0",
155 "rate-select1",
167 /* t_start_up (SFF-8431) or t_init (SFF-8472) is the time required for a
168 * non-cooled module to initialise its laser safety circuitry. We wait
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul-14x14-evk.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/media/video-interfaces.h>
9 stdout-path = &uart1;
17 backlight_display: backlight-display {
18 compatible = "pwm-backlight";
20 brightness-levels = <0 4 8 16 32 64 128 255>;
21 default-brightness-level = <6>;
26 reg_sd1_vmmc: regulator-sd1-vmmc {
27 compatible = "regulator-fixed";
28 regulator-name = "VSD_3V3";
[all …]
H A Dimx6sx-sdb.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
13 compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
16 stdout-path = &uart1;
24 backlight_display: backlight-display {
25 compatible = "pwm-backlight";
27 brightness-levels = <0 4 8 16 32 64 128 255>;
28 default-brightness-level = <6>;
[all …]
H A Dimx7d-sdb.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 /dts-v1/;
11 compatible = "fsl,imx7d-sdb", "fsl,imx7d";
19 stdout-path = &uart1;
27 gpio-keys {
28 compatible = "gpio-keys";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_gpio_keys>;
32 key-volume-up {
36 wakeup-source;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dphy-miphy28lp.txt1 STMicroelectronics STi MIPHY28LP PHY binding
4 This binding describes a miphy device that is used to control PHY hardware
8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
12 Required nodes : A sub-node is required for each channel the controller
14 'reg' and 'reg-names' properties are used inside these
19 - #phy-cells : Should be 1 (See second example)
21 - PHY_TYPE_SATA
22 - PHY_TYPE_PCI
23 - PHY_TYPE_USB3
[all …]
H A Dsocionext,uniphier-usb3ss-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro4-usb3-ssphy
[all …]
/openbmc/linux/arch/mips/boot/dts/xilfpga/
H A Dnexys4ddr.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
14 stdout-path = "serial0:115200n8";
22 cpuintc: interrupt-controller {
23 #address-cells = <0>;
24 #interrupt-cells = <1>;
25 interrupt-controller;
26 compatible = "mti,cpu-interrupt-controller";
29 axi_intc: interrupt-controller@10200000 {
30 #interrupt-cells = <1>;
[all …]
/openbmc/linux/arch/mips/boot/dts/ingenic/
H A Djz4780.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
4 #include <dt-bindings/dma/jz4780-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
21 clock-names = "cpu";
[all …]
H A Djz4770.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
6 #address-cells = <1>;
7 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
16 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
20 clock-names = "cpu";
24 cpuintc: interrupt-controller {
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a-iot.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2021-2022 NXP
7 /dts-v1/;
11 model = "LS1021A-IOT Board";
12 compatible = "fsl,ls1021a-iot", "fsl,ls1021a";
14 sys_mclk: clock-mclk {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <24576000>;
20 reg_3p3v: regulator-3V3 {
[all …]
H A Dls1021a-twr.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
7 /dts-v1/;
12 compatible = "fsl,ls1021a-twr", "fsl,ls1021a";
20 sys_mclk: clock-mclk {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <24576000>;
27 compatible = "regulator-fixed";
28 regulator-name = "3P3V";
[all …]
H A Dls1021a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
7 /dts-v1/;
12 compatible = "fsl,ls1021a-qds", "fsl,ls1021a";
22 sys_mclk: clock-mclk {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <24576000>;
29 compatible = "regulator-fixed";
30 regulator-name = "3P3V";
[all …]
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU
15 #include <linux/phy.h>
31 /* CLOCK feed to PHY*/
36 /* Ethernet PHY interface selection in register SYSCFG Configuration
37 *------------------------------------------
39 *------------------------------------------
41 *------------------------------------------
43 *------------------------------------------
45 *------------------------------------------
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/openbmc/linux/drivers/net/ethernet/atheros/atl1c/
H A Datl1c_hw.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
37 * 00-0B-6A-F6-00-DC in atl1c_hw_set_mac_addr()
78 /* MAC-address from BIOS is the 1st priority */ in atl1c_get_permanent_address()
79 if (atl1c_read_current_addr(hw, hw->perm_mac_addr)) in atl1c_get_permanent_address()
85 if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) { in atl1c_get_permanent_address()
95 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2) { in atl1c_get_permanent_address()
116 return -1; in atl1c_get_permanent_address()
119 if ((hw->nic_type == athr_l1c || hw->nic_type == athr_l2c)) { in atl1c_get_permanent_address()
134 if (atl1c_read_current_addr(hw, hw->perm_mac_addr)) in atl1c_get_permanent_address()
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2018-2021 NXP
11 /dts-v1/;
12 #include "fsl-ls1028a.dtsi"
16 compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
38 stdout-path = "serial0:115200n8";
46 sys_mclk: clock-mclk {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <25000000>;
[all …]
H A Dimx8ulp-evk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
12 compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
15 stdout-path = &lpuart5;
23 reserved-memory {
24 #address-cells = <2>;
25 #size-cells = <2>;
29 compatible = "shared-dma-pool";
32 linux,cma-default;
35 m33_reserved: noncacheable-section@a8600000 {
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Drx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2015-2017 Intel Deutschland GmbH
10 /* API for pre-9000 hardware */
26 * struct iwl_rx_phy_info - phy info
28 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
29 * @cfg_phy_cnt: configurable DSP phy data byte count
30 * @stat_id: configurable DSP phy data set ID
34 * @beacon_time_stamp: beacon at on-air rise
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dkirkwood-netxbig.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 * Based on netxbig_v2-setup.c,
14 #include <dt-bindings/leds/leds-netxbig.h>
16 #include "kirkwood-6281.dtsi"
21 stdout-path = &uart0;
33 #address-cells = <1>;
34 #size-cells = <1>;
35 compatible = "mxicy,mx25l4005a", "jedec,spi-nor", "spi-flash";
37 spi-max-frequency = <20000000>;
42 label = "u-boot";
[all …]
H A Dimx6sx-sdb.dtsi9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
17 compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
20 stdout-path = &uart1;
28 compatible = "pwm-backlight";
30 brightness-levels = <0 4 8 16 32 64 128 255>;
31 default-brightness-level = <6>;
34 gpio-keys {
35 compatible = "gpio-keys";
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-netxbig.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 * Based on netxbig_v2-setup.c,
14 #include <dt-bindings/leds/leds-netxbig.h>
16 #include "kirkwood-6281.dtsi"
21 stdout-path = &uart0;
33 #address-cells = <1>;
34 #size-cells = <1>;
35 compatible = "mxicy,mx25l4005a", "jedec,spi-nor";
37 spi-max-frequency = <20000000>;
42 label = "u-boot";
[all …]
/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dwhale2.dtsi6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/clock/sprd,sc9860-clk.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "simple-bus";
18 #address-cells = <2>;
19 #size-cells = <2>;
67 ap-apb {
68 compatible = "simple-bus";
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_phy.c27 * This file implements basic dp phy functionality such as enable/disable phy
29 * and update software state representing current phy status such as current
41 link->ctx->logger
49 if (link->sync_lt_in_progress) in dpcd_write_rx_power_ctrl()
64 link->cur_link_settings = *link_settings; in dp_enable_link_phy()
65 link->dc->hwss.enable_dp_link_output(link, link_res, signal, in dp_enable_link_phy()
74 struct dc *dc = link->ctx->dc; in dp_disable_link_phy()
76 if (!link->wa_flags.dp_keep_receiver_powered && in dp_disable_link_phy()
77 !link->skip_implict_edp_power_control) in dp_disable_link_phy()
80 dc->hwss.disable_link_output(link, link_res, signal); in dp_disable_link_phy()
[all …]
/openbmc/linux/drivers/nfc/pn533/
H A Duart.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for NXP PN532 NFC Chip - UART transport layer
38 * no-op to the chip.
52 struct pn532_uart_phy *pn532 = dev->phy; in pn532_uart_send_frame()
56 out->data, out->len, false); in pn532_uart_send_frame()
58 pn532->cur_out_buf = out; in pn532_uart_send_frame()
59 if (pn532->send_wakeup) { in pn532_uart_send_frame()
60 err = serdev_device_write(pn532->serdev, in pn532_uart_send_frame()
67 if (pn532->send_wakeup == PN532_SEND_LAST_WAKEUP) in pn532_uart_send_frame()
68 pn532->send_wakeup = PN532_SEND_NO_WAKEUP; in pn532_uart_send_frame()
[all …]

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