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12

/openbmc/linux/Documentation/devicetree/bindings/net/
H A Drenesas,ether.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,ether.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: ethernet-controller.yaml#
13 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
18 - items:
19 - enum:
20 - renesas,gether-r8a7740 # device is a part of R8A7740 SoC
21 - renesas,gether-r8a77980 # device is a part of R8A77980 SoC
[all …]
H A Drenesas,etheravb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
15 - items:
16 - enum:
17 - renesas,etheravb-r8a7742 # RZ/G1H
18 - renesas,etheravb-r8a7743 # RZ/G1M
19 - renesas,etheravb-r8a7744 # RZ/G1N
20 - renesas,etheravb-r8a7745 # RZ/G1E
[all …]
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7743-sk-rzg1m.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the SK-RZG1M board
5 * Copyright (C) 2016-2017 Cogent Embedded, Inc.
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
13 model = "SK-RZG1M";
14 compatible = "renesas,sk-rzg1m", "renesas,r8a7743";
22 stdout-path = "serial0:115200n8";
37 clock-frequency = <20000000>;
46 ether_pins: ether {
[all …]
H A Dr8a7745-sk-rzg1e.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the SK-RZG1E board
5 * Copyright (C) 2016-2017 Cogent Embedded, Inc.
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
13 model = "SK-RZG1E";
14 compatible = "renesas,sk-rzg1e", "renesas,r8a7745";
22 stdout-path = "serial0:115200n8";
32 clock-frequency = <20000000>;
41 ether_pins: ether {
[all …]
H A Dr8a7742-iwg21d-q7-dbcm-ca.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the iWave-RZ/G1H Qseven board development
9 /dts-v1/;
11 #include <dt-bindings/media/video-interfaces.h>
13 #include "r8a7742-iwg21d-q7.dts"
16 model = "iWave Systems RZ/G1H Qseven development platform with camera add-on";
24 ethernet1 = &ether;
27 mclk_cam1: mclk-cam1 {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
[all …]
H A Dr8a7790-stout.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
23 stdout-path = "serial0:115200n8";
32 compatible = "gpio-leds";
47 fixedregulator3v3: regulator-3v3 {
48 compatible = "regulator-fixed";
49 regulator-name = "fixed-3.3V";
50 regulator-min-microvolt = <3300000>;
[all …]
H A Dr8a7794-alt.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
30 stdout-path = "serial0:115200n8";
38 d3_3v: regulator-d3-3v {
39 compatible = "regulator-fixed";
40 regulator-name = "D3.3V";
41 regulator-min-microvolt = <3300000>;
42 regulator-max-microvolt = <3300000>;
[all …]
H A Dr8a7794-silk.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2014-2015 Renesas Solutions Corp.
7 * Copyright (C) 2014-2015 Cogent Embedded, Inc.
11 * SSI-AK4643
13 * SW1: 2-1: AK4643
14 * 2-3: ADV7511
21 /dts-v1/;
23 #include <dt-bindings/gpio/gpio.h>
24 #include <dt-bindings/input/input.h>
40 stdout-path = "serial0:115200n8";
[all …]
H A Dr8a7791-porter.dts1 // SPDX-License-Identifier: GPL-2.0
9 * SSI-AK4642
11 * JP3: 2-1: AK4642
12 * 2-3: ADV7511
19 /dts-v1/;
21 #include <dt-bindings/gpio/gpio.h>
37 stdout-path = "serial0:115200n8";
50 vcc_sdhi0: regulator-vcc-sdhi0 {
51 compatible = "regulator-fixed";
53 regulator-name = "SDHI0 Vcc";
[all …]
H A Dr8a7793-gose.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2015 Renesas Electronics Corporation
9 * SSI-AK4643
36 /dts-v1/;
38 #include <dt-bindings/gpio/gpio.h>
39 #include <dt-bindings/input/input.h>
59 stdout-path = "serial0:115200n8";
68 compatible = "gpio-keys";
70 pinctrl-0 = <&keyboard_pins>;
71 pinctrl-names = "default";
[all …]
H A Dr8a7791-koelsch.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2013-2014 Renesas Solutions Corp.
11 * SSI-AK4643
38 /dts-v1/;
40 #include <dt-bindings/gpio/gpio.h>
41 #include <dt-bindings/input/input.h>
63 stdout-path = "serial0:115200n8";
77 #address-cells = <1>;
78 #size-cells = <1>;
82 compatible = "gpio-keys";
[all …]
H A Dr8a7790-lager.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
7 * Copyright (C) 2015-2016 Renesas Electronics Corporation
11 * SSI-AK4643
38 /dts-v1/;
40 #include <dt-bindings/gpio/gpio.h>
41 #include <dt-bindings/input/input.h>
63 stdout-path = "serial0:115200n8";
77 #address-cells = <1>;
78 #size-cells = <1>;
[all …]
H A Dr8a7742-iwg21d-q7.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the iWave-RZ/G1H Qseven board
9 * SSI-SGTL5000
31 /dts-v1/;
32 #include "r8a7742-iwg21m.dtsi"
33 #include <dt-bindings/pwm/pwm.h>
36 model = "iWave Systems RainboW-G21D-Qseven board based on RZ/G1H";
47 stdout-path = "serial2:115200n8";
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dr8a7790-stout.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
23 stdout-path = "serial0:115200n8";
32 compatible = "gpio-leds";
47 fixedregulator3v3: regulator-3v3 {
48 compatible = "regulator-fixed";
49 regulator-name = "fixed-3.3V";
50 regulator-min-microvolt = <3300000>;
[all …]
H A Dr8a7794-alt.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
26 stdout-path = "serial0:115200n8";
34 d3_3v: regulator-d3-3v {
35 compatible = "regulator-fixed";
36 regulator-name = "D3.3V";
37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>;
39 regulator-boot-on;
[all …]
H A Dr8a7794-silk.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2014-2015 Renesas Solutions Corp.
7 * Copyright (C) 2014-2015 Cogent Embedded, Inc.
11 * SSI-AK4643
13 * SW1: 2-1: AK4643
14 * 2-3: ADV7511
21 /dts-v1/;
23 #include <dt-bindings/gpio/gpio.h>
24 #include <dt-bindings/input/input.h>
38 stdout-path = "serial0:115200n8";
[all …]
H A Dr8a7791-porter.dts1 // SPDX-License-Identifier: GPL-2.0
9 * SSI-AK4642
11 * JP3: 2-1: AK4642
12 * 2-3: ADV7511
19 /dts-v1/;
21 #include <dt-bindings/gpio/gpio.h>
35 stdout-path = "serial0:115200n8";
48 vcc_sdhi0: regulator-vcc-sdhi0 {
49 compatible = "regulator-fixed";
51 regulator-name = "SDHI0 Vcc";
[all …]
H A Dr8a7793-gose.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2015 Renesas Electronics Corporation
9 * SSI-AK4643
36 /dts-v1/;
38 #include <dt-bindings/gpio/gpio.h>
39 #include <dt-bindings/input/input.h>
56 stdout-path = "serial0:115200n8";
64 gpio-keys {
65 compatible = "gpio-keys";
67 key-1 {
[all …]
H A Dr8a7791-koelsch.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2013-2014 Renesas Solutions Corp.
11 * SSI-AK4643
38 /dts-v1/;
40 #include <dt-bindings/gpio/gpio.h>
41 #include <dt-bindings/input/input.h>
60 stdout-path = "serial0:115200n8";
74 #address-cells = <1>;
75 #size-cells = <1>;
79 compatible = "gpio-keys";
[all …]
H A Dr8a7790-lager.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
7 * Copyright (C) 2015-2016 Renesas Electronics Corporation
11 * SSI-AK4643
38 /dts-v1/;
40 #include <dt-bindings/gpio/gpio.h>
41 #include <dt-bindings/input/input.h>
60 stdout-path = "serial0:115200n8";
74 #address-cells = <1>;
75 #size-cells = <1>;
[all …]
/openbmc/linux/drivers/net/ethernet/intel/e1000e/
H A Dregs.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
7 #define E1000_CTRL 0x00000 /* Device Control - RW */
8 #define E1000_STATUS 0x00008 /* Device Status - RO */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_FLA 0x0001C /* Flash Access - RW */
13 #define E1000_MDIC 0x00020 /* MDI Control - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
[all …]
/openbmc/linux/drivers/net/ethernet/i825xx/
H A Dsun3_82586.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * copyrights (c) 1994 by Michael Hipp (hippm@informatik.uni-tuebingen.de)
11 * crynwr-packet-driver by Russ Nelson
12 * Garret A. Wollman's i82586-driver for BSD
53 char *iscp; /* pointer to the iscp-block */
65 char *scb_base; /* base-address of all 16-bit offsets */
79 unsigned short crc_errs; /* CRC-Error counter */
89 #define RUC_NOP 0x0000 /* NOP-command */
96 #define CUC_NOP 0x00 /* NOP-command */
114 #define STAT_CNA 0x20 /* CU left active state */
[all …]
/openbmc/linux/drivers/net/ethernet/intel/igb/
H A De1000_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
7 #define E1000_CTRL 0x00000 /* Device Control - RW */
8 #define E1000_STATUS 0x00008 /* Device Status - RO */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_MDIC 0x00020 /* MDI Control - RW */
13 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
[all …]
/openbmc/linux/drivers/net/ethernet/intel/igc/
H A Digc_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define IGC_CTRL 0x00000 /* Device Control - RW */
9 #define IGC_STATUS 0x00008 /* Device Status - RO */
10 #define IGC_EECD 0x00010 /* EEPROM/Flash Control - RW */
11 #define IGC_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define IGC_MDIC 0x00020 /* MDI Control - RW */
13 #define IGC_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
14 #define IGC_VET 0x00038 /* VLAN Ether Type - RW */
19 #define IGC_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
20 #define IGC_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
[all …]
/openbmc/linux/drivers/net/ethernet/renesas/
H A Dsh_eth.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
6 * Copyright (C) 2008-2014 Renesas Solutions Corp.
7 * Copyright (C) 2013-2017 Cogent Embedded, Inc.
15 #include <linux/dma-mapping.h>
19 #include <linux/mdio-bitbang.h>
44 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
53 __diag_ignore(GCC, 8, "-Woverride-init",
350 u16 offset = mdp->reg_offset[enum_index]; in sh_eth_write()
355 iowrite32(data, mdp->addr + offset); in sh_eth_write()
[all …]

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