Searched full:equalization (Results 1 – 12 of 12) sorted by relevance
44 * @TS_CHANNEL_EQUALIZATION: State for channel equalization193 * equalization, symbol lock, and interlane alignment. The remaining 2 bytes1030 /* delay for the channel equalization phase. */ in get_training_delay()1241 * check_channel_equalization() - Check channel equalization success1243 * @lane_count: The number of lanes for which to check channel equalization1247 * that the channel equalization sequence during link training was successful -1248 * the RX device has achieved channel equalization, symbol lock, and interlane1251 * Return: 0 if channel equalization was successful on all lanes in question,1275 /* All (lane_count) lanes have achieved channel equalization. */ in check_channel_equalization()1466 * training_state_channel_equalization() - Run channel equalization part of[all …]
154 /* training pattern 2 used for channel equalization */157 * training pattern 3 used for channel equalization for cores with DP
14 * @SRDSCR0_TXEQA_MASK: Bitmask for the TXEQA (transmit equalization for17 * @SRDSCR0_TXEQE_MASK: Bitmask for the TXEQE (transmit equalization for
510 u32 rec0; /* Receive Equalization Control 0 */511 u32 rec1; /* Receive Equalization Control 1 */512 u32 tec0; /* Transmit Equalization Control 0 */
619 u32 recr0; /* 0x810 Receive Equalization Control */621 u32 tecr0; /* 0x818 Transmit Equalization Control */
383 u32 recr0; /* 0x810 Receive Equalization Control */385 u32 tecr0; /* 0x818 Transmit Equalization Control */
1149 #define PCI_SECPCI_LE_CTRL 0x0c /* Lane Equalization Control Register */1152 #define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */1158 #define PCI_PL_32GT_LE_CTRL 0x20 /* Lane Equalization Control Register */1161 #define PCI_PL_64GT_LE_CTRL 0x20 /* Lane Equalization Control Register */
24 equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and
554 /* channel equalization loop */ in rk_edp_link_train_ce()
199 /* Config update polarity equalization */ in comphy_pcie_power_up()1328 /* Force FFE (Feed Forward Equalization) to 5G */ in comphy_sfi_power_up()
2604 u32 recr0; /* 0x810 Receive Equalization Control */2606 u32 tecr0; /* 0x818 Transmit Equalization Control */2665 u32 tecr0; /* TX Equalization Control Reg 0 */
1217 debug("dp: channel equalization failed\n"); in tegra_dc_dp_full_link_training()