/openbmc/linux/arch/riscv/boot/dts/starfive/ |
H A D | jh7110-starfive-visionfive-2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT 7 /dts-v1/; 9 #include "jh7110-pinfunc.h" 10 #include <dt-bindings/gpio/gpio.h> 26 stdout-path = "serial0:115200n8"; 30 timebase-frequency = <4000000>; 38 gpio-restart { 39 compatible = "gpio-restart"; 46 clock-frequency = <74250000>; 50 clock-frequency = <125000000>; [all …]
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H A D | jh7100-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT 7 /dts-v1/; 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/leds/common.h> 11 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h> 19 stdout-path = "serial0:115200n8"; 23 timebase-frequency = <6250000>; 32 compatible = "gpio-leds"; 34 led-ack { 38 linux,default-trigger = "heartbeat"; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
H A D | nvidia,tegra-pinmux-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra-pinmux-common.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jonathan Hunter <jonathanh@nvidia.com> 14 Please refer to pinctrl-bindings.txt in this directory for details of the 22 pin configuration parameters, such as pull-up, tristate, drive strength, 46 $ref: /schemas/types.yaml#/definitions/string-array 57 description: Pull-down/up setting to apply to the pin. [all …]
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H A D | nvidia,tegra210-pinmux.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra210-pinmux.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 const: nvidia,tegra210-pinmux 19 - description: APB_MISC_GP_*_PADCTRL register (pad control) 20 - description: PINMUX_AUX_* registers (pinmux) 23 "^pinmux(-[a-z0-9-_]+)?$": [all …]
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H A D | nvidia,tegra114-pinmux.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra114-pinmux.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 const: nvidia,tegra114-pinmux 19 - description: pad control registers 20 - description: mux registers 23 "^pinmux(-[a-z0-9-_]+)?$": [all …]
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H A D | nvidia,tegra30-pinmux.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra30-pinmux.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 const: nvidia,tegra30-pinmux 19 - description: pad control registers 20 - description: mux registers 23 "^pinmux(-[a-z0-9-_]+)?$": [all …]
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H A D | nvidia,tegra124-pinmux.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra124-pinmux.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 14 Tegra30 pinctrl binding, as described in nvidia,tegra20-pinmux.yaml and 15 nvidia,tegra30-pinmux.yaml. In fact, this document assumes that binding as a 21 - const: nvidia,tegra124-pinmux 22 - items: [all …]
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H A D | nuvoton,npcm7xx-pinctrl.txt | 3 The Nuvoton BMC NPCM7XX Pin Controller multi-function routed through 9 - #address-cells : should be 1. 10 - #size-cells : should be 1. 11 - compatible : "nuvoton,npcm750-pinctrl" for Poleg NPCM7XX. 12 - ranges : defines mapping ranges between pin controller node (parent) 19 Required GPIO Bank subnode-properties: 20 - reg : specifies physical base address and size of the GPIO 22 - gpio-controller : Marks the device node as a GPIO controller. 23 - #gpio-cells : Must be <2>. The first cell is the gpio pin number 25 - interrupts : contain the GPIO bank interrupt with flags for falling edge. [all …]
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/openbmc/linux/Documentation/devicetree/bindings/regulator/ |
H A D | maxim,max8973.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Krzysztof Kozlowski <krzk@kernel.org> 13 - $ref: regulator.yaml# 18 - maxim,max8973 19 - maxim,max77621 21 junction-warn-millicelsius: 30 maxim,dvs-gpio: 35 maxim,dvs-default-state: [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | rk3399-gru-chromebook.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Google Gru-Chromebook shared properties 8 #include "rk3399-gru.dtsi" 11 pp900_ap: pp900-ap { 12 compatible = "regulator-fixed"; 13 regulator-name = "pp900_ap"; 16 regulator-always-on; 17 regulator-boot-on; 18 regulator-min-microvolt = <900000>; 19 regulator-max-microvolt = <900000>; [all …]
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/openbmc/linux/include/dt-bindings/pinctrl/ |
H A D | pinctrl-tegra.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 14 * Enable/disable for diffeent dt properties. This is applicable for 15 * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain, 16 * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt. 31 /* Rising/Falling slew rate */
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/openbmc/u-boot/include/dt-bindings/pinctrl/ |
H A D | pinctrl-tegra.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 14 * Enable/disable for diffeent dt properties. This is applicable for 15 * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain, 16 * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt. 31 /* Rising/Falling slew rate */
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/openbmc/linux/arch/arm64/boot/dts/rockchip/ |
H A D | rk3399-gru-chromebook.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Google Gru-Chromebook shared properties 8 #include "rk3399-gru.dtsi" 11 pp900_ap: pp900-ap { 12 compatible = "regulator-fixed"; 13 regulator-name = "pp900_ap"; 16 regulator-always-on; 17 regulator-boot-on; 18 regulator-min-microvolt = <900000>; 19 regulator-max-microvolt = <900000>; [all …]
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/openbmc/linux/arch/arm/boot/dts/nvidia/ |
H A D | tegra114-roth.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/input.h> 15 linux,initrd-start = <0x82000000>; 16 linux,initrd-end = <0x82800000>; 24 trusted-foundations { 25 compatible = "tlm,trusted-foundations"; 26 tlm,version-major = <2>; 27 tlm,version-minor = <8>; 40 avdd-dsi-csi-supply = <&vdd_1v2_ap>; [all …]
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H A D | tegra114-dalmore.dts | 1 // SPDX-License-Identifier: GPL-2.0 7 /dts-v1/; 9 #include <dt-bindings/input/input.h> 23 stdout-path = "serial0:115200n8"; 34 hdmi-supply = <&vdd_5v0_hdmi>; 35 vdd-supply = <&vdd_hdmi_reg>; 36 pll-supply = <&palmas_smps3_reg>; 38 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 39 nvidia,hpd-gpio = 46 avdd-dsi-csi-supply = <&avdd_1v2_reg>; [all …]
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H A D | tegra30-asus-nexus7-grouper-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #include <dt-bindings/input/gpio-keys.h> 4 #include <dt-bindings/input/input.h> 5 #include <dt-bindings/power/summit,smb347-charger.h> 6 #include <dt-bindings/thermal/thermal.h> 9 #include "tegra30-cpu-opp.dtsi" 10 #include "tegra30-cpu-opp-microvolt.dtsi" 11 #include "tegra30-asus-lvds-display.dtsi" 27 * pre-existing /chosen node to be available to insert the 33 trusted-foundations { [all …]
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H A D | tegra124-venice2.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/input.h> 18 stdout-path = "serial0:115200n8"; 29 vdd-supply = <&vdd_3v3_hdmi>; 30 pll-supply = <&vdd_hdmi_pll>; 31 hdmi-supply = <&vdd_5v0_hdmi>; 33 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 34 nvidia,hpd-gpio = 41 avdd-io-hdmi-dp-supply = <&vdd_1v05_run>; [all …]
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H A D | tegra30-asus-transformer-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #include <dt-bindings/input/gpio-keys.h> 4 #include <dt-bindings/input/input.h> 5 #include <dt-bindings/thermal/thermal.h> 8 #include "tegra30-cpu-opp.dtsi" 9 #include "tegra30-cpu-opp-microvolt.dtsi" 12 chassis-type = "convertible"; 31 * pre-existing /chosen node to be available to insert the 37 trusted-foundations { 38 compatible = "tlm,trusted-foundations"; [all …]
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H A D | tegra30-pegatron-chagall.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/gpio-keys.h> 5 #include <dt-bindings/input/input.h> 6 #include <dt-bindings/thermal/thermal.h> 9 #include "tegra30-cpu-opp.dtsi" 10 #include "tegra30-cpu-opp-microvolt.dtsi" 11 #include "tegra30-asus-lvds-display.dtsi" 16 chassis-type = "tablet"; 35 * pre-existing /chosen node to be available to insert the [all …]
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H A D | tegra20-asus-tf101.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/atmel-maxtouch.h> 5 #include <dt-bindings/input/gpio-keys.h> 6 #include <dt-bindings/input/input.h> 7 #include <dt-bindings/thermal/thermal.h> 10 #include "tegra20-cpu-opp.dtsi" 11 #include "tegra20-cpu-opp-microvolt.dtsi" 16 chassis-type = "convertible"; 33 * pre-existing /chosen node to be available to insert the [all …]
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H A D | tegra20-acer-a500-picasso.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/atmel-maxtouch.h> 5 #include <dt-bindings/input/gpio-keys.h> 6 #include <dt-bindings/input/input.h> 7 #include <dt-bindings/thermal/thermal.h> 10 #include "tegra20-cpu-opp.dtsi" 11 #include "tegra20-cpu-opp-microvolt.dtsi" 32 * pre-existing /chosen node to be available to insert the 41 reserved-memory { [all …]
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/openbmc/linux/arch/arm/boot/dts/st/ |
H A D | stm32mp135f-dk.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved 7 /dts-v1/; 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/leds/common.h> 12 #include <dt-bindings/regulator/st,stm32mp13-regulator.h> 15 #include "stm32mp13-pinctrl.dtsi" 18 model = "STMicroelectronics STM32MP135F-DK Discovery Board"; 19 compatible = "st,stm32mp135f-dk", "st,stm32mp135"; [all …]
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H A D | stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 3 * Copyright (c) STMicroelectronics 2019 - All Rights Reserved 8 /dts-v1/; 10 #include "stm32mp157a-microgea-stm32mp1.dtsi" 11 #include "stm32mp15-pinctrl.dtsi" 12 #include "stm32mp15xxaa-pinctrl.dtsi" 13 #include <dt-bindings/gpio/gpio.h> 17 compatible = "engicam,microgea-stm32mp1-microdev2.0-of7", 18 "engicam,microgea-stm32mp1", "st,stm32mp157"; 26 stdout-path = "serial0:115200n8"; [all …]
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/openbmc/linux/drivers/pinctrl/ |
H A D | pinctrl-at91.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 6 * Parallel I/O Controller (PIO) - System peripherals registers. 12 #define PIO_PER 0x00 /* Enable Register */ 15 #define PIO_OER 0x10 /* Output Enable Register */ 18 #define PIO_IFER 0x20 /* Glitch Input Filter Enable */ 25 #define PIO_IER 0x40 /* Interrupt Enable Register */ 29 #define PIO_MDER 0x50 /* Multi-driver Enable Register */ 30 #define PIO_MDDR 0x54 /* Multi-driver Disable Register */ 31 #define PIO_MDSR 0x58 /* Multi-driver Status Register */ 32 #define PIO_PUDR 0x60 /* Pull-up Disable Register */ [all …]
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/openbmc/linux/arch/arm64/boot/dts/nvidia/ |
H A D | tegra132-norrin.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/input.h> 18 stdout-path = "serial0:115200n8"; 30 vdd-supply = <&vdd_3v3_hdmi>; 31 pll-supply = <&vdd_hdmi_pll>; 32 hdmi-supply = <&vdd_5v0_hdmi>; 34 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 35 nvidia,hpd-gpio = 42 avdd-io-hdmi-dp-supply = <&vdd_3v3_hdmi>; [all …]
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