12025cf9eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2b758df2eSLaxman Dewangan /* 3b758df2eSLaxman Dewangan * This header provides constants for Tegra pinctrl bindings. 4b758df2eSLaxman Dewangan * 5b758df2eSLaxman Dewangan * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 6b758df2eSLaxman Dewangan * 7b758df2eSLaxman Dewangan * Author: Laxman Dewangan <ldewangan@nvidia.com> 8b758df2eSLaxman Dewangan */ 9b758df2eSLaxman Dewangan 10b758df2eSLaxman Dewangan #ifndef _DT_BINDINGS_PINCTRL_TEGRA_H 11b758df2eSLaxman Dewangan #define _DT_BINDINGS_PINCTRL_TEGRA_H 12b758df2eSLaxman Dewangan 13b758df2eSLaxman Dewangan /* 14b758df2eSLaxman Dewangan * Enable/disable for diffeent dt properties. This is applicable for 15b758df2eSLaxman Dewangan * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain, 16b758df2eSLaxman Dewangan * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt. 17b758df2eSLaxman Dewangan */ 18b758df2eSLaxman Dewangan #define TEGRA_PIN_DISABLE 0 19b758df2eSLaxman Dewangan #define TEGRA_PIN_ENABLE 1 20b758df2eSLaxman Dewangan 21b758df2eSLaxman Dewangan #define TEGRA_PIN_PULL_NONE 0 22b758df2eSLaxman Dewangan #define TEGRA_PIN_PULL_DOWN 1 23b758df2eSLaxman Dewangan #define TEGRA_PIN_PULL_UP 2 24b758df2eSLaxman Dewangan 25b758df2eSLaxman Dewangan /* Low power mode driver */ 26b758df2eSLaxman Dewangan #define TEGRA_PIN_LP_DRIVE_DIV_8 0 27b758df2eSLaxman Dewangan #define TEGRA_PIN_LP_DRIVE_DIV_4 1 28b758df2eSLaxman Dewangan #define TEGRA_PIN_LP_DRIVE_DIV_2 2 29b758df2eSLaxman Dewangan #define TEGRA_PIN_LP_DRIVE_DIV_1 3 30b758df2eSLaxman Dewangan 31b758df2eSLaxman Dewangan /* Rising/Falling slew rate */ 32b758df2eSLaxman Dewangan #define TEGRA_PIN_SLEW_RATE_FASTEST 0 33b758df2eSLaxman Dewangan #define TEGRA_PIN_SLEW_RATE_FAST 1 34b758df2eSLaxman Dewangan #define TEGRA_PIN_SLEW_RATE_SLOW 2 35b758df2eSLaxman Dewangan #define TEGRA_PIN_SLEW_RATE_SLOWEST 3 36b758df2eSLaxman Dewangan 37b758df2eSLaxman Dewangan #endif 38