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/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dsprd,gpio-eic.yaml5 $id: http://devicetree.org/schemas/gpio/sprd,gpio-eic.yaml#
8 title: Unisoc EIC controller
16 The EIC is the abbreviation of external interrupt controller, which can
17 be used only in input mode. The Spreadtrum platform has 2 EIC controllers,
18 one is in digital chip, and another one is in PMIC. The digital chip EIC
19 controller contains 4 sub-modules, i.e. EIC-debounce, EIC-latch, EIC-async and
20 EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub-
23 The EIC-debounce sub-module provides up to 8 source input signal
32 The EIC-latch sub-module is used to latch some special power down signals
33 and generate interrupts, since the EIC-latch does not depend on the APB
[all …]
/openbmc/linux/drivers/irqchip/
H A Dirq-mchp-eic.c28 * struct mchp_eic - EIC private data structure
32 * @irqs: irqs b/w eic and gic
45 static struct mchp_eic *eic; variable
51 tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_mask()
53 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_mask()
62 tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_unmask()
64 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_unmask()
74 tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_set_type()
96 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_set_type()
103 irq_set_irq_wake(eic->irqs[d->hwirq], on); in mchp_eic_irq_set_wake()
[all …]
H A Dirq-mips-gic.c82 /* All local interrupts are routable in EIC mode. */ in gic_local_irq_is_routable()
721 /* Enable or disable EIC */ in gic_cpu_startup()
794 /* Always use vector 1 in EIC mode */ in gic_of_init()
H A DMakefile121 obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o
/openbmc/linux/drivers/gpio/
H A Dgpio-ep93xx.c54 struct ep93xx_gpio_irq_chip *eic; member
68 return egc->eic; in to_ep93xx_gpio_irq_chip()
83 struct ep93xx_gpio_irq_chip *eic) in ep93xx_gpio_update_int_params() argument
85 writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); in ep93xx_gpio_update_int_params()
87 writeb_relaxed(eic->int_type2, in ep93xx_gpio_update_int_params()
88 epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET); in ep93xx_gpio_update_int_params()
90 writeb_relaxed(eic->int_type1, in ep93xx_gpio_update_int_params()
91 epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET); in ep93xx_gpio_update_int_params()
93 writeb_relaxed(eic->int_unmasked & eic->int_enabled, in ep93xx_gpio_update_int_params()
94 epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); in ep93xx_gpio_update_int_params()
[all …]
H A Dgpio-eic-sprd.c16 /* EIC registers definition */
53 * The digital-chip EIC controller can support maximum 3 banks, and each bank
63 * The Spreadtrum EIC (external interrupt controller) can be used only in
66 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
67 * debounce EIC, latch EIC, async EIC and sync EIC,
69 * The debounce EIC is used to capture the input signals' stable status
74 * The latch EIC is used to latch some special power down signals and
75 * generate interrupts, since the latch EIC does not depend on the APB clock
78 * The async EIC uses a 32k clock to capture the short signals (microsecond
81 * The EIC-sync is similar with GPIO's input function, which is a synchronized
[all …]
H A Dgpio-pmic-eic-sprd.c15 /* EIC registers definition */
27 * The PMIC EIC controller only has one bank, and each bank now can contain
48 * struct sprd_pmic_eic - PMIC EIC controller
51 * @offset: the EIC controller's offset address of the PMIC.
52 * @reg: the array to cache the EIC registers.
54 * @irq: the interrupt number of the PMIC EIC conteroller.
189 * Will set the trigger level according to current EIC level in sprd_pmic_eic_irq_set_type()
231 /* Generate trigger start pulse for debounce EIC */ in sprd_pmic_eic_bus_sync_unlock()
256 dev_warn(chip->parent, "PMIC EIC level was changed.\n"); in sprd_pmic_eic_toggle_trigger()
263 /* Generate trigger start pulse for debounce EIC */ in sprd_pmic_eic_toggle_trigger()
[all …]
H A DMakefile57 obj-$(CONFIG_GPIO_EIC_SPRD) += gpio-eic-sprd.o
131 obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio-pmic-eic-sprd.o
H A DKconfig250 tristate "Spreadtrum EIC support"
255 Say yes here to support Spreadtrum EIC device.
1392 tristate "Spreadtrum PMIC EIC support"
1397 Say yes here to support Spreadtrum PMIC EIC device.
/openbmc/linux/drivers/hwmon/
H A Dsht21.c36 * @eic: cached electronic identification code text
45 char eic[18]; member
164 u8 eic[8]; in eic_read() local
186 eic[2] = rx[0]; in eic_read()
187 eic[3] = rx[2]; in eic_read()
188 eic[4] = rx[4]; in eic_read()
189 eic[5] = rx[6]; in eic_read()
197 eic[0] = rx[3]; in eic_read()
198 eic[1] = rx[4]; in eic_read()
199 eic[6] = rx[0]; in eic_read()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmicrochip,sama7g5-eic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/microchip,sama7g5-eic.yaml#
19 - microchip,sama7g5-eic
61 eic: interrupt-controller@e1628000 {
62 compatible = "microchip,sama7g5-eic";
H A Dmti,gic.yaml43 route interrupts. This property is ignored if the CPU is started in EIC
/openbmc/linux/arch/mips/include/asm/mips-boards/
H A Dmaltaint.h42 * Interrupts 96..127 are used for Soc-it EIC interrupts
46 /* SOC-it EIC interrupt offsets */
/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dwhale2.dtsi202 compatible = "sprd,sc9860-eic-debounce";
212 compatible = "sprd,sc9860-eic-latch";
222 compatible = "sprd,sc9860-eic-async";
232 compatible = "sprd,sc9860-eic-sync";
H A Dsc2731.dtsi56 compatible = "sprd,sc2731-eic";
/openbmc/linux/arch/s390/kvm/
H A Dintercept.c304 u16 eic = vcpu->arch.sie_block->eic; in handle_external_interrupt() local
323 if ((eic == EXT_IRQ_CLK_COMP || eic == EXT_IRQ_CPU_TIMER) && in handle_external_interrupt()
327 switch (eic) { in handle_external_interrupt()
H A Dinterrupt.c496 vcpu->arch.sie_block->eic = EXT_IRQ_CPU_TIMER; in __deliver_cpu_timer()
520 vcpu->arch.sie_block->eic = EXT_IRQ_CLK_COMP; in __deliver_ckc()
786 vcpu->arch.sie_block->eic = EXT_IRQ_EMERGENCY_SIG; in __deliver_emergency_signal()
820 vcpu->arch.sie_block->eic = EXT_IRQ_EXTERNAL_CALL; in __deliver_external_call()
978 vcpu->arch.sie_block->eic = EXT_IRQ_SERVICE_SIG; in write_sclp()
/openbmc/linux/Documentation/hwmon/
H A Dsht21.rst55 eic
/openbmc/qemu/hw/intc/
H A Dmips_gic.c229 /* EIC isn't supported */ in gic_write_vp()
239 /* EIC isn't supported */ in gic_write_vp()
322 /* EIC isn't supported */ in gic_write()
/openbmc/linux/drivers/net/ethernet/renesas/
H A Dravb.h148 EIC = 0x0358, enumerator
406 /* EIC */
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dsama7g5.dtsi650 eic: interrupt-controller@e1628000 { label
651 compatible = "microchip,sama7g5-eic";
/openbmc/linux/drivers/clk/sprd/
H A Dsc9863a-clk.c1152 static SPRD_SC_GATE_CLK_HW(eic_eb, "eic-eb", &aon_apb.common.hw, 0x0,
1242 static SPRD_SC_GATE_CLK_HW(eic_rtc_eb, "eic-rtc-eb", &aon_apb.common.hw,
1244 static SPRD_SC_GATE_CLK_HW(eic_rtcdv5_eb, "eic-rtcdv5-eb", &aon_apb.common.hw,
H A Dsc9860-clk.c854 static SPRD_SC_GATE_CLK(eic_eb, "eic-eb", "aon-apb", 0x0,
974 static SPRD_SC_GATE_CLK(eic_rtc_eb, "eic-rtc-eb", "aon-apb", 0x10,
976 static SPRD_SC_GATE_CLK(eic_rtcdv5_eb, "eic-rtcdv5-eb", "aon-apb", 0x10,
/openbmc/linux/arch/s390/include/asm/
H A Dkvm_host.h302 __u16 eic; /* 0x00c6 */ member
/openbmc/qemu/hw/net/
H A Digb_core.c881 uint32_t eic = 0; in igb_start_xmit() local
903 eic |= igb_txdesc_writeback(core, base, &desc, txi); in igb_start_xmit()
906 if (eic) { in igb_start_xmit()
907 igb_raise_interrupts(core, EICR, eic); in igb_start_xmit()

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