1384740dcSRalf Baechle /* 20b271f56SSteven J. Hill * This file is subject to the terms and conditions of the GNU General Public 30b271f56SSteven J. Hill * License. See the file "COPYING" in the main directory of this archive 4384740dcSRalf Baechle * for more details. 5384740dcSRalf Baechle * 60b271f56SSteven J. Hill * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved. 70b271f56SSteven J. Hill * Carsten Langgaard <carstenl@mips.com> 80b271f56SSteven J. Hill * Steven J. Hill <sjhill@mips.com> 9384740dcSRalf Baechle */ 10384740dcSRalf Baechle #ifndef _MIPS_MALTAINT_H 11384740dcSRalf Baechle #define _MIPS_MALTAINT_H 12384740dcSRalf Baechle 13384740dcSRalf Baechle /* 14384740dcSRalf Baechle * Interrupts 0..15 are used for Malta ISA compatible interrupts 15384740dcSRalf Baechle */ 16384740dcSRalf Baechle #define MALTA_INT_BASE 0 17384740dcSRalf Baechle 18384740dcSRalf Baechle /* CPU interrupt offsets */ 19384740dcSRalf Baechle #define MIPSCPU_INT_SW0 0 20384740dcSRalf Baechle #define MIPSCPU_INT_SW1 1 21384740dcSRalf Baechle #define MIPSCPU_INT_MB0 2 22384740dcSRalf Baechle #define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0 2318743d27SAndrew Bresticker #define MIPSCPU_INT_GIC MIPSCPU_INT_MB0 /* GIC chained interrupt */ 24384740dcSRalf Baechle #define MIPSCPU_INT_MB1 3 25384740dcSRalf Baechle #define MIPSCPU_INT_SMI MIPSCPU_INT_MB1 26384740dcSRalf Baechle #define MIPSCPU_INT_MB2 4 27384740dcSRalf Baechle #define MIPSCPU_INT_MB3 5 28384740dcSRalf Baechle #define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 29384740dcSRalf Baechle #define MIPSCPU_INT_MB4 6 30384740dcSRalf Baechle #define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4 31384740dcSRalf Baechle 32384740dcSRalf Baechle /* 33aa827b74SAndrew Bresticker * Interrupts 96..127 are used for Soc-it Classic interrupts 34384740dcSRalf Baechle */ 35aa827b74SAndrew Bresticker #define MSC01C_INT_BASE 96 36384740dcSRalf Baechle 37384740dcSRalf Baechle /* SOC-it Classic interrupt offsets */ 38384740dcSRalf Baechle #define MSC01C_INT_TMR 0 39384740dcSRalf Baechle #define MSC01C_INT_PCI 1 40384740dcSRalf Baechle 41384740dcSRalf Baechle /* 42aa827b74SAndrew Bresticker * Interrupts 96..127 are used for Soc-it EIC interrupts 43384740dcSRalf Baechle */ 44aa827b74SAndrew Bresticker #define MSC01E_INT_BASE 96 45384740dcSRalf Baechle 46384740dcSRalf Baechle /* SOC-it EIC interrupt offsets */ 47384740dcSRalf Baechle #define MSC01E_INT_SW0 1 48384740dcSRalf Baechle #define MSC01E_INT_SW1 2 49384740dcSRalf Baechle #define MSC01E_INT_MB0 3 50384740dcSRalf Baechle #define MSC01E_INT_I8259A MSC01E_INT_MB0 51384740dcSRalf Baechle #define MSC01E_INT_MB1 4 52384740dcSRalf Baechle #define MSC01E_INT_SMI MSC01E_INT_MB1 53384740dcSRalf Baechle #define MSC01E_INT_MB2 5 54384740dcSRalf Baechle #define MSC01E_INT_MB3 6 55384740dcSRalf Baechle #define MSC01E_INT_COREHI MSC01E_INT_MB3 56384740dcSRalf Baechle #define MSC01E_INT_MB4 7 57384740dcSRalf Baechle #define MSC01E_INT_CORELO MSC01E_INT_MB4 58384740dcSRalf Baechle #define MSC01E_INT_TMR 8 59384740dcSRalf Baechle #define MSC01E_INT_PCI 9 60384740dcSRalf Baechle #define MSC01E_INT_PERFCTR 10 61384740dcSRalf Baechle #define MSC01E_INT_CPUCTR 11 62384740dcSRalf Baechle 63384740dcSRalf Baechle #endif /* !(_MIPS_MALTAINT_H) */ 64