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/openbmc/qemu/hw/intc/
H A Daspeed_vic.c9 * the COPYING file in the top-level directory.
19 * member), but must cope with access offset values in multiples of 4 passed to
21 * provided offset to understand whether the access is requesting the lower or
24 * Additionally, the "Interrupt Enable", "Edge Status" and "Software Interrupt"
27 * read-modify-write sequence).
47 uint64_t new = (s->raw & s->enable); in aspeed_vic_update()
50 flags = new & s->select; in aspeed_vic_update()
52 qemu_set_irq(s->fiq, !!flags); in aspeed_vic_update()
54 flags = new & ~s->select; in aspeed_vic_update()
56 qemu_set_irq(s->irq, !!flags); in aspeed_vic_update()
[all …]
/openbmc/linux/drivers/gpio/
H A Dgpio-rda.c1 // SPDX-License-Identifier: GPL-2.0-only
44 static inline void rda_gpio_update(struct gpio_chip *chip, unsigned int offset, in rda_gpio_update() argument
48 void __iomem *base = rda_gpio->base; in rda_gpio_update()
52 spin_lock_irqsave(&rda_gpio->lock, flags); in rda_gpio_update()
56 tmp |= BIT(offset); in rda_gpio_update()
58 tmp &= ~BIT(offset); in rda_gpio_update()
61 spin_unlock_irqrestore(&rda_gpio->lock, flags); in rda_gpio_update()
68 void __iomem *base = rda_gpio->base; in rda_gpio_irq_mask()
69 u32 offset = irqd_to_hwirq(data); in rda_gpio_irq_mask() local
72 value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT; in rda_gpio_irq_mask()
[all …]
H A Dgpio-sa1100.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-sa1100/gpio.c
5 * Generic SA-1100 GPIO handling
40 static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset) in sa1100_gpio_get() argument
42 return readl_relaxed(sa1100_gpio_chip(chip)->membase + R_GPLR) & in sa1100_gpio_get()
43 BIT(offset); in sa1100_gpio_get()
46 static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value) in sa1100_gpio_set() argument
50 writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg); in sa1100_gpio_set()
53 static int sa1100_get_direction(struct gpio_chip *chip, unsigned offset) in sa1100_get_direction() argument
55 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; in sa1100_get_direction()
[all …]
H A Dgpio-pl061.c1 // SPDX-License-Identifier: GPL-2.0-only
63 static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) in pl061_get_direction() argument
67 if (readb(pl061->base + GPIODIR) & BIT(offset)) in pl061_get_direction()
73 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) in pl061_direction_input() argument
79 raw_spin_lock_irqsave(&pl061->lock, flags); in pl061_direction_input()
80 gpiodir = readb(pl061->base + GPIODIR); in pl061_direction_input()
81 gpiodir &= ~(BIT(offset)); in pl061_direction_input()
82 writeb(gpiodir, pl061->base + GPIODIR); in pl061_direction_input()
83 raw_spin_unlock_irqrestore(&pl061->lock, flags); in pl061_direction_input()
88 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, in pl061_direction_output() argument
[all …]
H A Dgpio-mxc.c1 // SPDX-License-Identifier: GPL-2.0+
8 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
86 .edge_sel_reg = -EINVAL,
101 .edge_sel_reg = -EINVAL,
123 #define GPIO_DR (port->hwdata->dr_reg)
124 #define GPIO_GDIR (port->hwdata->gdir_reg)
125 #define GPIO_PSR (port->hwdata->psr_reg)
126 #define GPIO_ICR1 (port->hwdata->icr1_reg)
127 #define GPIO_ICR2 (port->hwdata->icr2_reg)
128 #define GPIO_IMR (port->hwdata->imr_reg)
[all …]
H A Dgpio-tqmx86.c1 // SPDX-License-Identifier: GPL-2.0
3 * TQ-Systems TQMx86 PLD GPIO driver
23 #define TQMX86_NGPO 4 /* 0-3 - output */
24 #define TQMX86_NGPI 4 /* 4-7 - input */
25 #define TQMX86_DIR_INPUT_MASK 0xf0 /* 0-3 - output, 4-7 - input */
56 return ioread8(gd->io_base + reg); in tqmx86_gpio_read()
62 iowrite8(val, gd->io_base + reg); in tqmx86_gpio_write()
65 static int tqmx86_gpio_get(struct gpio_chip *chip, unsigned int offset) in tqmx86_gpio_get() argument
69 return !!(tqmx86_gpio_read(gpio, TQMX86_GPIOD) & BIT(offset)); in tqmx86_gpio_get()
72 static void tqmx86_gpio_set(struct gpio_chip *chip, unsigned int offset, in tqmx86_gpio_set() argument
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H A Dgpio-stmpe.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2010
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
41 static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset) in stmpe_gpio_get() argument
44 struct stmpe *stmpe = stmpe_gpio->stmpe; in stmpe_gpio_get()
45 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)]; in stmpe_gpio_get()
46 u8 mask = BIT(offset % 8); in stmpe_gpio_get()
56 static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) in stmpe_gpio_set() argument
59 struct stmpe *stmpe = stmpe_gpio->stmpe; in stmpe_gpio_set()
61 u8 reg = stmpe->regs[which + (offset / 8)]; in stmpe_gpio_set()
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H A Dgpio-mxs.c1 // SPDX-License-Identifier: GPL-2.0+
7 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
25 #define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
26 #define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
27 #define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
28 #define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
29 #define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
30 #define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
31 #define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
32 #define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
[all …]
H A Dgpio-rcar.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas R-Car GPIO Support
61 #define EDGLEVEL 0x24 /* Edge/level Select Register */
64 #define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
71 return ioread32(p->base + offs); in gpio_rcar_read()
77 iowrite32(value, p->base + offs); in gpio_rcar_write()
122 * "Setting Edge-Sensitive Interrupt Input Mode" and in gpio_rcar_config_interrupt_input_mode()
123 * "Setting Level-Sensitive Interrupt Input Mode" in gpio_rcar_config_interrupt_input_mode()
126 spin_lock_irqsave(&p->lock, flags); in gpio_rcar_config_interrupt_input_mode()
131 /* Configure edge or level trigger in EDGLEVEL */ in gpio_rcar_config_interrupt_input_mode()
[all …]
H A Dgpio-grgpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 * See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
45 /* Structure for an irq of the core - called an underlying irq */
56 s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
83 * obtains from this driver. An index value of -1 for a certain gpio
90 static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset, in grgpio_set_imask() argument
93 struct gpio_chip *gc = &priv->gc; in grgpio_set_imask()
96 priv->imask |= BIT(offset); in grgpio_set_imask()
98 priv->imask &= ~BIT(offset); in grgpio_set_imask()
99 gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask); in grgpio_set_imask()
[all …]
/openbmc/linux/drivers/gpu/drm/ast/
H A Dast_dp501.c1 // SPDX-License-Identifier: GPL-2.0
15 release_firmware(ast->dp501_fw); in ast_release_firmware()
16 ast->dp501_fw = NULL; in ast_release_firmware()
24 ret = request_firmware(&ast->dp501_fw, "ast_dp501_fw.bin", dev->dev); in ast_load_dp501_microcode()
28 return devm_add_action_or_reset(dev->dev, ast_release_firmware, ast); in ast_load_dp501_microcode()
192 if (ast->config_mode != ast_use_p2a) in ast_backup_fw()
213 if (ast->config_mode != ast_use_p2a) in ast_launch_m68k()
219 if (ast->dp501_fw_addr) { in ast_launch_m68k()
220 fw_addr = ast->dp501_fw_addr; in ast_launch_m68k()
223 if (!ast->dp501_fw && in ast_launch_m68k()
[all …]
/openbmc/u-boot/doc/
H A DI2C_Edge_Conditions1 I2C Edge Conditions:
7 The edge condition is as follows:
16 3) The I2C controller writes the offset.
22 4) device address "EEPROM interprets this as offset"
23 5) Offset in device, "EEPROM interprets this as data to write"
26 write rubbish into itself, i.e. the "offset" will be interpreted
30 -----
33 This reset edge condition could possibly be present in every I2C
38 bit-banging I2C driver (common/soft_i2c.c) as this already includes
46 Tue, 5 Mar 2002 23:02:19 -0500 (Wed 05:02 MET)
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,sc7280-mss-pil.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sibi Sankar <quic_sibis@quicinc.com>
19 - qcom,sc7280-mss-pil
23 - description: MSS QDSP6 registers
24 - description: RMB registers
26 reg-names:
28 - const: qdsp6
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H A Dqcom,msm8996-mss-pil.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,msm8996-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Sibi Sankar <quic_sibis@quicinc.com>
20 - qcom,msm8996-mss-pil
21 - qcom,msm8998-mss-pil
22 - qcom,sdm660-mss-pil
23 - qcom,sdm845-mss-pil
[all …]
H A Dqcom,sc7180-mss-pil.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7180-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sibi Sankar <quic_sibis@quicinc.com>
19 - qcom,sc7180-mss-pil
23 - description: MSS QDSP6 registers
24 - description: RMB registers
26 reg-names:
28 - const: qdsp6
[all …]
H A Dqcom,sc7280-adsp-pil.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-adsp-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
19 - qcom,sc7280-adsp-pil
23 - description: qdsp6ss register
24 - description: efuse q6ss register
28 - description: Phandle to apps_smmu node with sid mask
32 - description: Watchdog interrupt
[all …]
H A Dqcom,smd-edge.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,smd-edge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SMD Edge communication channel nodes
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
14 some sort - or in SMD language an "edge". The name of the edges are not
18 that "edge". The names of the devices are not important. The properties of
24 const: smd-edge
29 - qcom,smd-channels
[all …]
H A Dqcom,msm8916-mss-pil.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,msm8916-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephan Gerhold <stephan@gerhold.net>
19 - enum:
20 - qcom,msm8909-mss-pil
21 - qcom,msm8916-mss-pil
22 - qcom,msm8953-mss-pil
23 - qcom,msm8974-mss-pil
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/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-at91.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Parallel I/O Controller (PIO) - System peripherals registers.
29 #define PIO_MDER 0x50 /* Multi-driver Enable Register */
30 #define PIO_MDDR 0x54 /* Multi-driver Disable Register */
31 #define PIO_MDSR 0x58 /* Multi-driver Status Register */
32 #define PIO_PUDR 0x60 /* Pull-up Disable Register */
33 #define PIO_PUER 0x64 /* Pull-up Enable Register */
34 #define PIO_PUSR 0x68 /* Pull-up Status Register */
45 #define PIO_PPDDR 0x90 /* Pad Pull-down Disable Register */
46 #define PIO_PPDER 0x94 /* Pad Pull-down Enable Register */
[all …]
/openbmc/linux/drivers/media/rc/
H A Dserial_ir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * serial_ir - Device driver that records pulse- and pause-lengths
6 * (space-lengths) between DDCD event on a serial port.
8 * Copyright (C) 1996,97 Ralph Metzler <rjkm@thp.uni-koeln.de>
13 * Copyright (C) 2016 Sean Young <sean@mess.org> (port to rc-core)
27 #include <media/rc-core.h>
36 void (*send_pulse)(unsigned int length, ktime_t edge);
55 static int sense = -1; /* -1 = auto, 0 = active high, 1 = active low */
59 static void send_pulse_irdeo(unsigned int length, ktime_t edge);
62 static void send_pulse_homebrew(unsigned int length, ktime_t edge);
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/openbmc/linux/fs/btrfs/
H A Dbackref.c1 // SPDX-License-Identifier: GPL-2.0
10 #include "disk-io.h"
14 #include "delayed-ref.h"
17 #include "tree-mod-log.h"
20 #include "extent-tree.h"
22 #include "tree-checker.h"
30 u64 offset; member
42 u64 offset = key->offset; in check_extent_in_eb() local
48 if (!ctx->ignore_extent_item_pos && in check_extent_in_eb()
56 if (ctx->extent_item_pos < data_offset || in check_extent_in_eb()
[all …]
/openbmc/linux/Documentation/virt/kvm/devices/
H A Dmpic.rst1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.0
10 - KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.2
20 KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
25 KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
27 "attr" is the byte offset into the MPIC register space. Accesses
28 must be 4-byte aligned.
33 KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
37 For edge-triggered interrupts: Writing 1 is considered an activating
38 edge, and writing 0 is ignored. Reading returns 1 if a previously
[all …]
/openbmc/linux/arch/mips/lantiq/
H A Dirq.c1 // SPDX-License-Identifier: GPL-2.0-only
23 /* register definitions - internal irqs */
32 /* register definitions - external irqs */
75 return -1; in ltq_eiu_get_irq()
80 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; in ltq_disable_irq() local
81 unsigned long im = offset / INT_NUM_IM_OFFSET; in ltq_disable_irq()
85 offset %= INT_NUM_IM_OFFSET; in ltq_disable_irq()
90 ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset), in ltq_disable_irq()
98 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; in ltq_mask_and_ack_irq() local
99 unsigned long im = offset / INT_NUM_IM_OFFSET; in ltq_mask_and_ack_irq()
[all …]
/openbmc/qemu/hw/gpio/
H A Domap_gpio.c4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 * Copyright (C) 2007-2009 Nokia Corporation
24 #include "hw/qdev-properties.h"
27 #include "qemu/error-report.h"
38 uint16_t edge; member
53 /* General-Purpose I/O of OMAP1 */
57 struct omap_gpio_s *s = &p->omap1; in omap_gpio_set()
58 uint16_t prev = s->inputs; in omap_gpio_set()
61 s->inputs |= 1 << line; in omap_gpio_set()
63 s->inputs &= ~(1 << line); in omap_gpio_set()
[all …]
/openbmc/u-boot/drivers/gpio/
H A Dgpio-rcar.c1 // SPDX-License-Identifier: GPL-2.0+
23 #define GPIO_EDGLEVEL 0x24 /* Edge/level Select Register */
25 #define GPIO_BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
36 static int rcar_gpio_get_value(struct udevice *dev, unsigned offset) in rcar_gpio_get_value() argument
39 const u32 bit = BIT(offset); in rcar_gpio_get_value()
45 if (readl(priv->regs + GPIO_INOUTSEL) & bit) in rcar_gpio_get_value()
46 return !!(readl(priv->regs + GPIO_OUTDT) & bit); in rcar_gpio_get_value()
48 return !!(readl(priv->regs + GPIO_INDT) & bit); in rcar_gpio_get_value()
51 static int rcar_gpio_set_value(struct udevice *dev, unsigned offset, in rcar_gpio_set_value() argument
57 setbits_le32(priv->regs + GPIO_OUTDT, BIT(offset)); in rcar_gpio_set_value()
[all …]

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