Lines Matching +full:edge +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2010
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
41 static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset) in stmpe_gpio_get() argument
44 struct stmpe *stmpe = stmpe_gpio->stmpe; in stmpe_gpio_get()
45 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)]; in stmpe_gpio_get()
46 u8 mask = BIT(offset % 8); in stmpe_gpio_get()
56 static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) in stmpe_gpio_set() argument
59 struct stmpe *stmpe = stmpe_gpio->stmpe; in stmpe_gpio_set()
61 u8 reg = stmpe->regs[which + (offset / 8)]; in stmpe_gpio_set()
62 u8 mask = BIT(offset % 8); in stmpe_gpio_set()
68 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB]) in stmpe_gpio_set()
75 unsigned offset) in stmpe_gpio_get_direction() argument
78 struct stmpe *stmpe = stmpe_gpio->stmpe; in stmpe_gpio_get_direction()
79 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); in stmpe_gpio_get_direction()
80 u8 mask = BIT(offset % 8); in stmpe_gpio_get_direction()
94 unsigned offset, int val) in stmpe_gpio_direction_output() argument
97 struct stmpe *stmpe = stmpe_gpio->stmpe; in stmpe_gpio_direction_output()
98 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)]; in stmpe_gpio_direction_output()
99 u8 mask = BIT(offset % 8); in stmpe_gpio_direction_output()
101 stmpe_gpio_set(chip, offset, val); in stmpe_gpio_direction_output()
107 unsigned offset) in stmpe_gpio_direction_input() argument
110 struct stmpe *stmpe = stmpe_gpio->stmpe; in stmpe_gpio_direction_input()
111 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)]; in stmpe_gpio_direction_input()
112 u8 mask = BIT(offset % 8); in stmpe_gpio_direction_input()
117 static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset) in stmpe_gpio_request() argument
120 struct stmpe *stmpe = stmpe_gpio->stmpe; in stmpe_gpio_request()
122 if (stmpe_gpio->norequest_mask & BIT(offset)) in stmpe_gpio_request()
123 return -EINVAL; in stmpe_gpio_request()
125 return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO); in stmpe_gpio_request()
144 int offset = d->hwirq; in stmpe_gpio_irq_set_type() local
145 int regoffset = offset / 8; in stmpe_gpio_irq_set_type()
146 int mask = BIT(offset % 8); in stmpe_gpio_irq_set_type()
149 return -EINVAL; in stmpe_gpio_irq_set_type()
152 if (stmpe_gpio->stmpe->partnum == STMPE801 || in stmpe_gpio_irq_set_type()
153 stmpe_gpio->stmpe->partnum == STMPE1600) in stmpe_gpio_irq_set_type()
157 stmpe_gpio->regs[REG_RE][regoffset] |= mask; in stmpe_gpio_irq_set_type()
159 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask; in stmpe_gpio_irq_set_type()
162 stmpe_gpio->regs[REG_FE][regoffset] |= mask; in stmpe_gpio_irq_set_type()
164 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask; in stmpe_gpio_irq_set_type()
174 mutex_lock(&stmpe_gpio->irq_lock); in stmpe_gpio_irq_lock()
181 struct stmpe *stmpe = stmpe_gpio->stmpe; in stmpe_gpio_irq_sync_unlock()
182 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); in stmpe_gpio_irq_sync_unlock()
201 if (stmpe->partnum == STMPE1600) { in stmpe_gpio_irq_sync_unlock()
202 stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]); in stmpe_gpio_irq_sync_unlock()
203 stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]); in stmpe_gpio_irq_sync_unlock()
208 if ((stmpe->partnum == STMPE801 || in stmpe_gpio_irq_sync_unlock()
209 stmpe->partnum == STMPE1600) && in stmpe_gpio_irq_sync_unlock()
214 u8 old = stmpe_gpio->oldregs[i][j]; in stmpe_gpio_irq_sync_unlock()
215 u8 new = stmpe_gpio->regs[i][j]; in stmpe_gpio_irq_sync_unlock()
220 stmpe_gpio->oldregs[i][j] = new; in stmpe_gpio_irq_sync_unlock()
221 stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new); in stmpe_gpio_irq_sync_unlock()
225 mutex_unlock(&stmpe_gpio->irq_lock); in stmpe_gpio_irq_sync_unlock()
232 int offset = d->hwirq; in stmpe_gpio_irq_mask() local
233 int regoffset = offset / 8; in stmpe_gpio_irq_mask()
234 int mask = BIT(offset % 8); in stmpe_gpio_irq_mask()
236 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask; in stmpe_gpio_irq_mask()
237 gpiochip_disable_irq(gc, offset); in stmpe_gpio_irq_mask()
244 int offset = d->hwirq; in stmpe_gpio_irq_unmask() local
245 int regoffset = offset / 8; in stmpe_gpio_irq_unmask()
246 int mask = BIT(offset % 8); in stmpe_gpio_irq_unmask()
248 gpiochip_enable_irq(gc, offset); in stmpe_gpio_irq_unmask()
249 stmpe_gpio->regs[REG_IE][regoffset] |= mask; in stmpe_gpio_irq_unmask()
254 unsigned offset, unsigned gpio) in stmpe_dbg_show_one() argument
257 struct stmpe *stmpe = stmpe_gpio->stmpe; in stmpe_dbg_show_one()
258 const char *label = gpiochip_is_requested(gc, offset); in stmpe_dbg_show_one()
259 bool val = !!stmpe_gpio_get(gc, offset); in stmpe_dbg_show_one()
260 u8 bank = offset / 8; in stmpe_dbg_show_one()
261 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank]; in stmpe_dbg_show_one()
262 u8 mask = BIT(offset % 8); in stmpe_dbg_show_one()
272 seq_printf(s, " gpio-%-3d (%-20.20s) out %s", in stmpe_dbg_show_one()
282 "edge-inactive", in stmpe_dbg_show_one()
283 "edge-asserted", in stmpe_dbg_show_one()
284 "not-supported" in stmpe_dbg_show_one()
287 "no-rising-edge-detection", in stmpe_dbg_show_one()
288 "rising-edge-detection", in stmpe_dbg_show_one()
289 "not-supported" in stmpe_dbg_show_one()
292 "no-falling-edge-detection", in stmpe_dbg_show_one()
293 "falling-edge-detection", in stmpe_dbg_show_one()
294 "not-supported" in stmpe_dbg_show_one()
302 switch (stmpe->partnum) { in stmpe_dbg_show_one()
308 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank]; in stmpe_dbg_show_one()
315 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank]; in stmpe_dbg_show_one()
316 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank]; in stmpe_dbg_show_one()
329 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank]; in stmpe_dbg_show_one()
341 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s", in stmpe_dbg_show_one()
345 irqen ? "IRQ-enabled" : "IRQ-disabled", in stmpe_dbg_show_one()
354 unsigned gpio = gc->base; in stmpe_dbg_show()
356 for (i = 0; i < gc->ngpio; i++, gpio++) { in stmpe_dbg_show()
363 .name = "stmpe-gpio",
378 struct stmpe *stmpe = stmpe_gpio->stmpe; in stmpe_gpio_irq()
380 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); in stmpe_gpio_irq()
393 if (stmpe->partnum == STMPE1600) in stmpe_gpio_irq()
394 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB]; in stmpe_gpio_irq()
396 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB]; in stmpe_gpio_irq()
403 int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i : in stmpe_gpio_irq()
404 num_banks - i - 1; in stmpe_gpio_irq()
405 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank]; in stmpe_gpio_irq()
415 int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain, in stmpe_gpio_irq()
425 * Edge detect register is not present on 801/1600/1801 in stmpe_gpio_irq()
427 if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 && in stmpe_gpio_irq()
428 stmpe->partnum != STMPE1801) { in stmpe_gpio_irq()
431 stmpe->regs[STMPE_IDX_GPEDR_MSB] + i, in stmpe_gpio_irq()
446 if (!stmpe_gpio->norequest_mask) in stmpe_init_irq_valid_mask()
451 if (stmpe_gpio->norequest_mask & BIT(i)) in stmpe_init_irq_valid_mask()
463 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent); in stmpe_gpio_probe()
464 struct device_node *np = pdev->dev.of_node; in stmpe_gpio_probe()
468 if (stmpe->num_gpios > MAX_GPIOS) { in stmpe_gpio_probe()
469 dev_err(&pdev->dev, "Need to increase maximum GPIO number\n"); in stmpe_gpio_probe()
470 return -EINVAL; in stmpe_gpio_probe()
473 stmpe_gpio = devm_kzalloc(&pdev->dev, sizeof(*stmpe_gpio), GFP_KERNEL); in stmpe_gpio_probe()
475 return -ENOMEM; in stmpe_gpio_probe()
477 mutex_init(&stmpe_gpio->irq_lock); in stmpe_gpio_probe()
479 stmpe_gpio->dev = &pdev->dev; in stmpe_gpio_probe()
480 stmpe_gpio->stmpe = stmpe; in stmpe_gpio_probe()
481 stmpe_gpio->chip = template_chip; in stmpe_gpio_probe()
482 stmpe_gpio->chip.ngpio = stmpe->num_gpios; in stmpe_gpio_probe()
483 stmpe_gpio->chip.parent = &pdev->dev; in stmpe_gpio_probe()
484 stmpe_gpio->chip.base = -1; in stmpe_gpio_probe()
487 stmpe_gpio->chip.dbg_show = stmpe_dbg_show; in stmpe_gpio_probe()
489 of_property_read_u32(np, "st,norequest-mask", in stmpe_gpio_probe()
490 &stmpe_gpio->norequest_mask); in stmpe_gpio_probe()
494 dev_info(&pdev->dev, in stmpe_gpio_probe()
495 "device configured in no-irq mode: " in stmpe_gpio_probe()
502 ret = devm_add_action_or_reset(&pdev->dev, stmpe_gpio_disable, stmpe); in stmpe_gpio_probe()
509 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, in stmpe_gpio_probe()
511 "stmpe-gpio", stmpe_gpio); in stmpe_gpio_probe()
513 dev_err(&pdev->dev, "unable to get irq: %d\n", ret); in stmpe_gpio_probe()
517 girq = &stmpe_gpio->chip.irq; in stmpe_gpio_probe()
520 girq->parent_handler = NULL; in stmpe_gpio_probe()
521 girq->num_parents = 0; in stmpe_gpio_probe()
522 girq->parents = NULL; in stmpe_gpio_probe()
523 girq->default_type = IRQ_TYPE_NONE; in stmpe_gpio_probe()
524 girq->handler = handle_simple_irq; in stmpe_gpio_probe()
525 girq->threaded = true; in stmpe_gpio_probe()
526 girq->init_valid_mask = stmpe_init_irq_valid_mask; in stmpe_gpio_probe()
529 return devm_gpiochip_add_data(&pdev->dev, &stmpe_gpio->chip, stmpe_gpio); in stmpe_gpio_probe()
535 .name = "stmpe-gpio",