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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dtlv320adcx140.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
11 - Andrew Davis <afd@ti.com>
14 The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15 PDM microphones recording), high-performance audio, analog-to-digital
28 - ti,tlv320adc3140
29 - ti,tlv320adc5140
30 - ti,tlv320adc6140
[all …]
/openbmc/linux/drivers/irqchip/
H A Dqcom-pdc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
45 #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base)
88 __pdc_enable_intr(d->hwirq, on); in pdc_enable_intr()
105 * GIC does not handle falling edge or active low. To allow falling edge and
107 * falling edge into a rising edge and active low into an active high.
111 * Rising edge sensitive NOT USED
112 * Falling edge sensitive LOW
113 * Dual Edge sensitive NOT USED
114 * Level sensitive active High HIGH
[all …]
H A Dirq-lpc32xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com>
37 return readl_relaxed(ic->base + reg); in lpc32xx_ic_read()
43 writel_relaxed(val, ic->base + reg); in lpc32xx_ic_write()
49 u32 val, mask = BIT(d->hwirq); in lpc32xx_irq_mask()
58 u32 val, mask = BIT(d->hwirq); in lpc32xx_irq_unmask()
67 u32 mask = BIT(d->hwirq); in lpc32xx_irq_ack()
75 u32 val, mask = BIT(d->hwirq); in lpc32xx_irq_set_type()
76 bool high, edge; in lpc32xx_irq_set_type() local
80 edge = true; in lpc32xx_irq_set_type()
[all …]
H A Dirq-aspeed-vic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015 - Ben Herrenschmidt, IBM Corp.
7 * Based on irq-vic.c:
9 * Copyright (C) 1999 - 2003 ARM Limited
32 * register set that interleaves "high" and "low". The offsets
33 * below are for the "low" register, add 4 to get to the high one
63 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR); in vic_init_hw()
64 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4); in vic_init_hw()
67 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR); in vic_init_hw()
68 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4); in vic_init_hw()
[all …]
/openbmc/qemu/hw/intc/
H A Daspeed_vic.c9 * the COPYING file in the top-level directory.
16 * The hardware uses 32bit registers to manage 51 IRQs, with low and high
18 * uses 64bit data types to store both low and high register values (in the one
24 * Additionally, the "Interrupt Enable", "Edge Status" and "Software Interrupt"
27 * read-modify-write sequence).
47 uint64_t new = (s->raw & s->enable); in aspeed_vic_update()
50 flags = new & s->select; in aspeed_vic_update()
52 qemu_set_irq(s->fiq, !!flags); in aspeed_vic_update()
54 flags = new & ~s->select; in aspeed_vic_update()
56 qemu_set_irq(s->irq, !!flags); in aspeed_vic_update()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dcavium-octeon-gpio.txt4 - compatible: "cavium,octeon-3860-gpio"
8 - reg: The base address of the GPIO unit's register bank.
10 - gpio-controller: This is a GPIO controller.
12 - #gpio-cells: Must be <2>. The first cell is the GPIO pin.
14 - interrupt-controller: The GPIO controller is also an interrupt
18 - #interrupt-cells: Must be <2>. The first cell is the GPIO pin
21 1 - edge triggered on the rising edge.
22 2 - edge triggered on the falling edge
23 4 - level triggered active high.
24 8 - level triggered active low.
[all …]
H A Dgpio-nmk.txt4 - compatible : Should be "st,nomadik-gpio".
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller.
7 - #gpio-cells : Should be two:
10 - bits[3:0] trigger type and level flags:
11 1 = low-to-high edge triggered.
12 2 = high-to-low edge triggered.
13 4 = active high level-sensitive.
14 8 = active low level-sensitive.
15 - gpio-controller : Marks the device node as a GPIO controller.
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Dm88ds3103.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 * enum m88ds3103_ts_mode - TS connection mode
47 * struct m88ds3103_platform_data - Platform data for the m88ds3103 driver
52 * @ts_clk_pol: TS clk polarity. 1-active at falling edge; 0-active at rising
53 * edge.
59 * @lnb_hv_pol: LNB H/V pin polarity. 0: pin high set to VOLTAGE_18, pin low to
60 * set VOLTAGE_13. 1: pin high set to VOLTAGE_13, pin low to set VOLTAGE_18.
61 * @lnb_en_pol: LNB enable pin polarity. 0: pin high to disable, pin low to
62 * enable. 1: pin high to enable, pin low to disable.
88 * struct m88ds3103_config - m88ds3102 configuration
[all …]
/openbmc/linux/Documentation/core-api/
H A Dgenericirq.rst7 :Copyright: |copy| 2005-2010: Thomas Gleixner
8 :Copyright: |copy| 2005-2006: Ingo Molnar
29 __do_IRQ() super-handler, which is able to deal with every type of
36 - Level type
38 - Edge type
40 - Simple type
44 - Fast EOI type
46 In the SMP world of the __do_IRQ() super-handler another type was
49 - Per CPU type
51 This split implementation of high-level IRQ handlers allows us to
[all …]
/openbmc/linux/drivers/media/rc/
H A Dserial_ir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * serial_ir - Device driver that records pulse- and pause-lengths
6 * (space-lengths) between DDCD event on a serial port.
8 * Copyright (C) 1996,97 Ralph Metzler <rjkm@thp.uni-koeln.de>
13 * Copyright (C) 2016 Sean Young <sean@mess.org> (port to rc-core)
27 #include <media/rc-core.h>
36 void (*send_pulse)(unsigned int length, ktime_t edge);
55 static int sense = -1; /* -1 = auto, 0 = active high, 1 = active low */
56 static bool txsense; /* 0 = active high, 1 = active low */
59 static void send_pulse_irdeo(unsigned int length, ktime_t edge);
[all …]
/openbmc/u-boot/drivers/video/
H A Dam335x-fb.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at> -
4 * B&R Industrial Automation GmbH - http://www.br-automation.com
17 * Matrix displays the edge timing is
22 * the rising edge of pixel clock (bit
25 * the falling edge of pixel clock (bit
29 * 0 = DE is low-active
30 * 1 = DE is high-active
33 * 0 = pix-clk is high-active
34 * 1 = pic-clk is low-active
[all …]
/openbmc/linux/drivers/iio/common/st_sensors/
H A Dst_sensors_trigger.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2012-2013 STMicroelectronics Inc.
19 * st_sensors_new_samples_available() - check if more samples came in
24 * false - no new samples available or read error
25 * true - new samples available
33 if (!sdata->sensor_settings->drdy_irq.stat_drdy.addr) in st_sensors_new_samples_available()
37 if (!indio_dev->active_scan_mask) in st_sensors_new_samples_available()
40 ret = regmap_read(sdata->regmap, in st_sensors_new_samples_available()
41 sdata->sensor_settings->drdy_irq.stat_drdy.addr, in st_sensors_new_samples_available()
44 dev_err(indio_dev->dev.parent, in st_sensors_new_samples_available()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/power/reset/
H A Dgpio-restart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
15 This binding supports level and edge triggered reset. At driver load time, the driver will
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
22 This will also cause an inactive->active edge condition, triggering positive edge triggered
23 reset. After a delay specified by active-delay, the GPIO is set to inactive, thus causing an
24 active->inactive edge, triggering negative edge triggered reset. After a delay specified by
[all …]
/openbmc/u-boot/doc/device-tree-bindings/video/
H A Ddisplay-timing.txt1 display-timing bindings
4 display-timings node
5 --------------------
8 - none
11 - native-mode: The native mode for the display, in case multiple modes are
15 --------------
18 - hactive, vactive: display resolution
19 - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters
21 vfront-porch, vback-porch, vsync-len: vertical display timing parameters in
23 - clock-frequency: display clock in Hz
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/panel/
H A Dpanel-timing.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-timing.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Sam Ravnborg <sam@ravnborg.org>
20 +-------+----------+-------------------------------------+----------+
24 +-------+----------+-------------------------------------+----------+
28 +-------+----------#######################################----------+
33 |<----->|<-------->#<-------+--------------------------->#<-------->|
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Datmel,aic.txt4 - compatible: Should be:
5 - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2",
7 - "microchip,<chip>-aic" where <chip> can be "sam9x60"
9 - interrupt-controller: Identifies the node as an interrupt controller.
10 - #interrupt-cells: The number of cells to define the interrupts. It should be 3.
14 1 = low-to-high edge triggered.
15 2 = high-to-low edge triggered.
16 4 = active high level-sensitive.
17 8 = active low level-sensitive.
19 Default flag for internal sources should be set to 4 (active high).
[all …]
H A Dsnps,archs-idu-intc.txt1 * ARC-HS Interrupt Distribution Unit
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
21 4 = active high level-sensitive <<< DEFAULT
22 8 = NOT SUPPORTED (active low level-sensitive)
30 core_intc: core-interrupt-controller {
[all …]
H A Dimg,pdc-intc.txt10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
/openbmc/linux/include/media/i2c/
H A Dtvp7002.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
6 * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
19 * struct tvp7002_config - Platform dependent data
21 * 0 - Data clocked out on rising edge of DATACLK signal
22 * 1 - Data clocked out on falling edge of DATACLK signal
24 * 0 - Active low HSYNC output, 1 - Active high HSYNC output
26 * 0 - Active low VSYNC output, 1 - Active high VSYNC output
27 *@fid_polarity: Active-high Field ID polarity.
28 * 0 - The field ID output is set to logic 1 for an odd field
[all …]
/openbmc/linux/drivers/clk/
H A Dclk-axi-clkgen.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2012-2013 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
11 #include <linux/clk-provider.h>
144 d_min = max_t(unsigned long, DIV_ROUND_UP(fin, limits->fpfd_max), 1); in axi_clkgen_calc_params()
145 d_max = min_t(unsigned long, fin / limits->fpfd_min, 80); in axi_clkgen_calc_params()
148 fvco_min_fract = limits->fvco_min << fract_shift; in axi_clkgen_calc_params()
149 fvco_max_fract = limits->fvco_max << fract_shift; in axi_clkgen_calc_params()
164 if (abs(f - fout) < abs(best_f - fout)) { in axi_clkgen_calc_params()
167 *best_m = m << (3 - fract_shift); in axi_clkgen_calc_params()
[all …]
/openbmc/qemu/include/hw/intc/
H A Daspeed_vic.h9 * the COPYING file in the top-level directory.
39 /* 0=edge, 1=level */
42 /* 0=single-edge, 1=dual-edge */
45 /* 0=low-sensitive/falling-edge, 1=high-sensitive/rising-edge */
/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Dmaxim-ds1302.txt1 * Maxim/Dallas Semiconductor DS-1302 RTC
5 The device uses the standard MicroWire half-duplex transfer timing.
7 edge. Master input is set by the RTC on the trailing edge and is sensed
12 - compatible : Should be "maxim,ds1302"
16 - reg : Should be address of the device chip select within
19 - spi-max-frequency : DS-1302 has 500 kHz if powered at 2.2V,
22 - spi-3wire : The device has a shared signal IN/OUT line.
24 - spi-lsb-first : DS-1302 requires least significant bit first
27 - spi-cs-high: DS-1302 has active high chip select line. This is
33 #address-cells = <1>;
[all …]
/openbmc/u-boot/doc/device-tree-bindings/gpio/
H A Dnvidia,tegra20-gpio.txt4 - compatible : "nvidia,tegra<chip>-gpio"
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller. For Tegra20,
9 - #gpio-cells : Should be two. The first cell is the pin number and the
11 - bit 0 specifies polarity (0 for normal, 1 for inverted)
12 - gpio-controller : Marks the device node as a GPIO controller.
13 - #interrupt-cells : Should be 2.
17 1 = low-to-high edge triggered.
18 2 = high-to-low edge triggered.
19 4 = active high level-sensitive.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dicpdas-lp8841-spi-rtc.txt1 * ICP DAS LP-8841 SPI Controller for RTC
3 ICP DAS LP-8841 contains a DS-1302 RTC. RTC is connected to an IO
6 The device uses the standard MicroWire half-duplex transfer timing.
8 edge. Master input is set by the RTC on the trailing edge and is sensed
13 - #address-cells: should be 1
15 - #size-cells: should be 0
17 - compatible: should be "icpdas,lp8841-spi-rtc"
19 - reg: should provide IO memory address
23 - There can be only one slave device.
25 - The spi slave node should claim the following flags which are
[all …]
/openbmc/linux/Documentation/input/devices/
H A Drotary-encoder.rst2 rotary-encoder - a generic driver for GPIO connected devices
8 --------
11 peripherals with two wires. The outputs are phase-shifted by 90 degrees
16 a stable state with both outputs high (half-period mode) and some have
17 a stable state in all steps (quarter-period mode).
33 |<-------->|
36 |<-->|
37 one step (half-period mode)
40 one step (quarter-period mode)
47 ----------------------
[all …]

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