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/openbmc/linux/drivers/nvmem/
H A Dsprd-efuse.c39 * The Spreadtrum AP efuse contains 2 parts: normal efuse and secure efuse,
40 * and we can only access the normal efuse in kernel. So define the normal
52 * when reading or writing data to efuse memory, the controller can save double
80 * efuse controller, so we need one hardware spinlock to synchronize between
83 static int sprd_efuse_lock(struct sprd_efuse *efuse) in sprd_efuse_lock() argument
87 mutex_lock(&efuse->mutex); in sprd_efuse_lock()
89 ret = hwspin_lock_timeout_raw(efuse->hwlock, in sprd_efuse_lock()
92 dev_err(efuse->dev, "timeout get the hwspinlock\n"); in sprd_efuse_lock()
93 mutex_unlock(&efuse->mutex); in sprd_efuse_lock()
100 static void sprd_efuse_unlock(struct sprd_efuse *efuse) in sprd_efuse_unlock() argument
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H A Dmeson-mx-efuse.c3 * Amlogic Meson6, Meson8 and Meson8b eFuse Driver
50 static void meson_mx_efuse_mask_bits(struct meson_mx_efuse *efuse, u32 reg, in meson_mx_efuse_mask_bits() argument
55 data = readl(efuse->base + reg); in meson_mx_efuse_mask_bits()
59 writel(data, efuse->base + reg); in meson_mx_efuse_mask_bits()
62 static int meson_mx_efuse_hw_enable(struct meson_mx_efuse *efuse) in meson_mx_efuse_hw_enable() argument
66 err = clk_prepare_enable(efuse->core_clk); in meson_mx_efuse_hw_enable()
70 /* power up the efuse */ in meson_mx_efuse_hw_enable()
71 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_hw_enable()
74 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL4, in meson_mx_efuse_hw_enable()
80 static void meson_mx_efuse_hw_disable(struct meson_mx_efuse *efuse) in meson_mx_efuse_hw_disable() argument
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H A Dsc27xx-efuse.c16 /* Efuse controller registers definition */
80 * efuse controller, so we need one hardware spinlock to synchronize between
83 static int sc27xx_efuse_lock(struct sc27xx_efuse *efuse) in sc27xx_efuse_lock() argument
87 mutex_lock(&efuse->mutex); in sc27xx_efuse_lock()
89 ret = hwspin_lock_timeout_raw(efuse->hwlock, in sc27xx_efuse_lock()
92 dev_err(efuse->dev, "timeout to get the hwspinlock\n"); in sc27xx_efuse_lock()
93 mutex_unlock(&efuse->mutex); in sc27xx_efuse_lock()
100 static void sc27xx_efuse_unlock(struct sc27xx_efuse *efuse) in sc27xx_efuse_unlock() argument
102 hwspin_unlock_raw(efuse->hwlock); in sc27xx_efuse_unlock()
103 mutex_unlock(&efuse->mutex); in sc27xx_efuse_unlock()
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H A Drockchip-efuse.c3 * Rockchip eFuse Driver
58 struct rockchip_efuse_chip *efuse = context; in rockchip_rk3288_efuse_read() local
62 ret = clk_prepare_enable(efuse->clk); in rockchip_rk3288_efuse_read()
64 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); in rockchip_rk3288_efuse_read()
68 writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
71 writel(readl(efuse->base + REG_EFUSE_CTRL) & in rockchip_rk3288_efuse_read()
73 efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
74 writel(readl(efuse->base + REG_EFUSE_CTRL) | in rockchip_rk3288_efuse_read()
76 efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
78 writel(readl(efuse->base + REG_EFUSE_CTRL) | in rockchip_rk3288_efuse_read()
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H A Djz4780-efuse.c3 * JZ4780 EFUSE Memory Support driver
10 * Currently supports JZ4780 efuse which has 8K programmable bit.
11 * Efuse is separated into seven segments as below:
72 struct jz4780_efuse *efuse = context; in jz4780_efuse_read() local
87 regmap_update_bits(efuse->map, JZ_EFUCTRL, in jz4780_efuse_read()
94 ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE, in jz4780_efuse_read()
99 dev_err(efuse->dev, "Time out while reading efuse data"); in jz4780_efuse_read()
103 ret = regmap_bulk_read(efuse->map, JZ_EFUDATA(0), in jz4780_efuse_read()
119 .name = "jz4780-efuse",
142 struct jz4780_efuse *efuse; in jz4780_efuse_probe() local
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H A DMakefile26 nvmem_jz4780_efuse-y := jz4780-efuse.o
36 nvmem_meson_efuse-y := meson-efuse.o
38 nvmem_meson_mx_efuse-y := meson-mx-efuse.o
41 obj-$(CONFIG_NVMEM_MTK_EFUSE) += nvmem_mtk-efuse.o
42 nvmem_mtk-efuse-y := mtk-efuse.o
56 nvmem_rockchip_efuse-y := rockchip-efuse.o
59 obj-$(CONFIG_NVMEM_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o
60 nvmem-sc27xx-efuse-y := sc27xx-efuse.o
66 nvmem_sprd_efuse-y := sprd-efuse.o
76 obj-$(CONFIG_NVMEM_UNIPHIER_EFUSE) += nvmem-uniphier-efuse.o
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H A DKconfig31 tristate "Apple eFuse support"
104 tristate "JZ4780 EFUSE Memory Support"
110 Say Y here to include support for JZ4780 efuse memory found on
157 tristate "Amlogic Meson GX eFuse Support"
160 This is a driver to retrieve specific values from the eFuse found on
167 tristate "Amlogic Meson6/Meson8/Meson8b eFuse Support"
170 This is a driver to retrieve specific values from the eFuse found on
184 tristate "Mediatek SoCs EFUSE support"
192 will be called efuse-mtk.
259 tristate "Rockchip eFuse Support"
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/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-delta-ahe50dc.dts8 efuse##n { \
10 vout-supply = <&efuse##n>; \
15 #define EFUSE(hexaddr, num) \ macro
16 efuse@##hexaddr { \
21 efuse##num: vout { \
22 regulator-name = __stringify(efuse##num##-reg); \
166 EFUSE(10, 03);
167 EFUSE(11, 04);
168 EFUSE(12, 01);
169 EFUSE(13, 02);
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/openbmc/linux/Documentation/devicetree/bindings/nvmem/
H A Drockchip-efuse.yaml4 $id: http://devicetree.org/schemas/nvmem/rockchip-efuse.yaml#
7 title: Rockchip eFuse
18 - rockchip,rk3066a-efuse
19 - rockchip,rk3188-efuse
20 - rockchip,rk3228-efuse
21 - rockchip,rk3288-efuse
22 - rockchip,rk3328-efuse
23 - rockchip,rk3368-efuse
24 - rockchip,rk3399-efuse
27 - rockchip,rockchip-efuse
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H A Dmediatek,efuse.yaml4 $id: http://devicetree.org/schemas/nvmem/mediatek,efuse.yaml#
7 title: MediaTek efuse
10 MediaTek's efuse is used for storing calibration data, it can be accessed
22 pattern: "^efuse@[0-9a-f]+$"
28 - mediatek,mt7622-efuse
29 - mediatek,mt7623-efuse
30 - mediatek,mt7986-efuse
31 - mediatek,mt8173-efuse
32 - mediatek,mt8183-efuse
33 - mediatek,mt8186-efuse
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H A Dsc27xx-efuse.txt1 = Spreadtrum SC27XX PMIC eFuse device tree bindings =
5 "sprd,sc2720-efuse"
6 "sprd,sc2721-efuse"
7 "sprd,sc2723-efuse"
8 "sprd,sc2730-efuse"
9 "sprd,sc2731-efuse"
10 - reg: Specify the address offset of efuse controller.
14 Are child nodes of eFuse, bindings of which as described in
29 efuse@380 {
30 compatible = "sprd,sc2731-efuse";
H A Damlogic,meson6-efuse.yaml4 $id: http://devicetree.org/schemas/nvmem/amlogic,meson6-efuse.yaml#
7 title: Amlogic Meson6 eFuse
19 - amlogic,meson6-efuse
20 - amlogic,meson8-efuse
21 - amlogic,meson8b-efuse
42 efuse: efuse@0 {
43 compatible = "amlogic,meson6-efuse";
H A Damlogic,meson-gxbb-efuse.yaml4 $id: http://devicetree.org/schemas/nvmem/amlogic,meson-gxbb-efuse.yaml#
7 title: Amlogic Meson GX eFuse
18 - const: amlogic,meson-gxbb-efuse
20 - const: amlogic,meson-gx-efuse
21 - const: amlogic,meson-gxbb-efuse
39 efuse: efuse {
40 compatible = "amlogic,meson-gxbb-efuse";
/openbmc/linux/Documentation/devicetree/bindings/fuse/
H A Dnvidia,tegra20-fuse.yaml17 - nvidia,tegra20-efuse
18 - nvidia,tegra30-efuse
19 - nvidia,tegra114-efuse
20 - nvidia,tegra124-efuse
21 - nvidia,tegra210-efuse
22 - nvidia,tegra186-efuse
23 - nvidia,tegra194-efuse
24 - nvidia,tegra234-efuse
27 - const: nvidia,tegra132-efuse
28 - const: nvidia,tegra124-efuse
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/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dti-abb-regulator.txt35 efuse: (see Optional properties)
36 RBB enable efuse Mask: (See Optional properties)
37 FBB enable efuse Mask: (See Optional properties)
38 Vset value efuse Mask: (See Optional properties)
47 - "efuse-address" - Contains efuse base address used to pick up ABB info.
49 "efuse-address" is required for this.
55 efuse: Mandatory if 'efuse-address' register is defined. Provides offset
56 from efuse-address to pick up ABB characteristics. Set to 0 if
57 'efuse-address' is not defined.
58 RBB enable efuse Mask: Optional if 'efuse-address' register is defined.
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/openbmc/linux/drivers/phy/mediatek/
H A Dphy-mtk-pcie.c36 * struct mtk_pcie_lane_efuse - eFuse data for each lane
40 * @lane_efuse_supported: software eFuse data is supported for this lane
52 * @sw_efuse_supported: support software to load eFuse data
65 * @sw_efuse_en: software eFuse enable status
67 * @efuse: pointer to eFuse data for each lane
77 struct mtk_pcie_lane_efuse *efuse; member
83 struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_set_lane()
106 * Initialize the phy by setting the efuse data.
136 struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_read_for_lane() local
142 ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_pmos); in mtk_pcie_efuse_read_for_lane()
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/openbmc/u-boot/arch/arm/mach-mvebu/
H A Defuse.c11 #include <asm/arch/efuse.h>
68 static int do_prog_efuse(struct mvebu_hd_efuse *efuse, in do_prog_efuse() argument
73 val.dwords.d[0] = readl(&efuse->bits_31_0); in do_prog_efuse()
74 val.dwords.d[1] = readl(&efuse->bits_63_32); in do_prog_efuse()
75 val.lock = readl(&efuse->bit64); in do_prog_efuse()
84 writel(val.dwords.d[0], &efuse->bits_31_0); in do_prog_efuse()
86 writel(val.dwords.d[1], &efuse->bits_63_32); in do_prog_efuse()
88 writel(val.lock, &efuse->bit64); in do_prog_efuse()
96 struct mvebu_hd_efuse *efuse; in prog_efuse() local
103 efuse = get_efuse_line(nr); in prog_efuse()
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/openbmc/u-boot/doc/device-tree-bindings/exynos/
H A Dtmu.txt14 - samsung,efuse-min-value : SOC efuse min value (Constant 40)
15 - efuse-value should be more than this value.
16 - samsung,efuse-value : SOC actual efuse value (Literal value)
19 - samsung,efuse-max-value : SoC max efuse value (Constant 100)
20 - efuse-value should be less than this value.
39 samsung,efuse-min-value = <40>;
40 samsung,efuse-value = <55>;
41 samsung,efuse-max-value = <100>;
/openbmc/u-boot/board/ti/dra7xx/
H A Devm.c376 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
377 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
385 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
386 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
387 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
388 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
396 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
397 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
398 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
399 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
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/openbmc/linux/drivers/cpufreq/
H A Dti-cpufreq.c57 unsigned long efuse);
77 unsigned long efuse) in amx3_efuse_xlate() argument
79 if (!efuse) in amx3_efuse_xlate()
80 efuse = opp_data->soc_data->efuse_fallback; in amx3_efuse_xlate()
82 return ~efuse; in amx3_efuse_xlate()
86 unsigned long efuse) in dra7_efuse_xlate() argument
91 * The efuse on dra7 and am57 parts contains a specific in dra7_efuse_xlate()
95 switch (efuse) { in dra7_efuse_xlate()
112 unsigned long efuse) in omap3_efuse_xlate() argument
115 return BIT(efuse); in omap3_efuse_xlate()
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/openbmc/u-boot/drivers/misc/
H A Drockchip-efuse.c3 * eFuse driver for Rockchip devices
31 u32 ctrl; /* 0x00 efuse control register */
32 u32 dout; /* 0x04 efuse data out register */
33 u32 rf; /* 0x08 efuse redundancy bit used register */
37 /* 0x14 efuse strobe finish control register */
73 printf("efuse-contents:\n"); in dump_efuses()
90 struct rockchip_efuse_regs *efuse = in rockchip_rk3399_efuse_read() local
103 /* cap to the size of the efuse block */ in rockchip_rk3399_efuse_read()
108 &efuse->ctrl); in rockchip_rk3399_efuse_read()
111 setbits_le32(&efuse->ctrl, in rockchip_rk3399_efuse_read()
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/openbmc/u-boot/board/compulab/cl-som-am57x/
H A Dspl.c164 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
165 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
172 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
173 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
174 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
175 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
182 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
183 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
184 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
185 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
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/openbmc/qemu/include/hw/nvram/
H A Dxlnx-efuse.h2 * QEMU model of the Xilinx eFuse core
33 #define TYPE_XLNX_EFUSE "xlnx-efuse"
69 * @s: the efuse object
70 * @bit: the efuse bit-address to read the data
78 * @s: the efuse object
79 * @bit: the efuse bit-address to be written a value of 1
87 * @s: the efuse object
89 * @start: the efuse bit-address (which must be multiple of 32) of the
101 * @s: the efuse object
103 * This function inspects a number of efuse bits at specific addresses
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/openbmc/u-boot/board/ti/am57xx/
H A Dboard.c324 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
325 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
333 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
334 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
335 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
336 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
344 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
345 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
346 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
347 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
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/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Defuse.c8 #include "efuse.h"
31 /* efuse header format
43 u32 physical_size = rtwdev->efuse.physical_size; in rtw_dump_logical_efuse_map()
44 u32 protect_size = rtwdev->efuse.protect_size; in rtw_dump_logical_efuse_map()
45 u32 logical_size = rtwdev->efuse.logical_size; in rtw_dump_logical_efuse_map()
90 u32 size = rtwdev->efuse.physical_size; in rtw_dump_physical_efuse_map()
149 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw_parse_efuse_map() local
150 u32 phy_size = efuse->physical_size; in rtw_parse_efuse_map()
151 u32 log_size = efuse->logical_size; in rtw_parse_efuse_map()
165 rtw_err(rtwdev, "failed to dump efuse physical map\n"); in rtw_parse_efuse_map()
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