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/openbmc/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi-gp-audio.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * dw-hdmi-gp-audio.c
5 * Copyright 2020-2022 NXP
12 #include <linux/dma-mapping.h>
17 #include <sound/hdmi-codec.h>
26 #include "dw-hdmi-audio.h"
28 #define DRIVER_NAME "dw-hdmi-gp-audio"
29 #define DRV_NAME "hdmi-gp-audio"
43 * The default mapping of ALSA channels to HDMI channels and speaker
44 * allocation bits. Note that we can't do channel remapping here -
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H A Ddw-hdmi-ahb-audio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DesignWare HDMI audio driver
5 * Written and tested against the Designware HDMI Tx found in iMX6.
21 #include "dw-hdmi-audio.h"
23 #define DRIVER_NAME "dw-hdmi-ahb-audio"
84 * The default mapping of ALSA channels to HDMI channels and speaker
85 * allocation bits. Note that we can't do channel remapping here -
88 * Mappings for alsa-lib pcm/surround*.conf files:
93 * Our mapping from ALSA channel to CEA686D speaker name and HDMI channel:
153 static void dw_hdmi_reformat_iec958(struct snd_dw_hdmi *dw, in dw_hdmi_reformat_iec958() argument
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
2 obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
3 obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
4 obj-$(CONFIG_DRM_DW_HDMI_GP_AUDIO) += dw-hdmi-gp-audio.o
5 obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
6 obj-$(CONFIG_DRM_DW_HDMI_CEC) += dw-hdmi-cec.o
8 obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw-mipi-dsi.o
H A Ddw-hdmi-i2s-audio.c1 // SPDX-License-Identifier: GPL-2.0
3 * dw-hdmi-i2s-audio.c
9 #include <linux/dma-mapping.h>
15 #include <sound/hdmi-codec.h>
17 #include "dw-hdmi.h"
18 #include "dw-hdmi-audio.h"
20 #define DRIVER_NAME "dw-hdmi-i2s-audio"
25 struct dw_hdmi *hdmi = audio->hdmi; in hdmi_write() local
27 audio->write(hdmi, val, offset); in hdmi_write()
32 struct dw_hdmi *hdmi = audio->hdmi; in hdmi_read() local
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H A Ddw-hdmi-cec.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Designware HDMI CEC driver
5 * Copyright (C) 2015-2017 Russell King.
17 #include <media/cec-notifier.h>
19 #include "dw-hdmi-cec.h"
55 struct dw_hdmi *hdmi; member
73 cec->ops->write(cec->hdmi, val, offset); in dw_hdmi_write()
78 return cec->ops->read(cec->hdmi, offset); in dw_hdmi_read()
86 cec->addresses = 0; in dw_hdmi_cec_log_addr()
88 cec->addresses |= BIT(logical_addr) | BIT(15); in dw_hdmi_cec_log_addr()
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/openbmc/linux/Documentation/devicetree/bindings/display/
H A Damlogic,meson-dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic specific extensions to the Synopsys Designware HDMI Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 - $ref: /schemas/sound/dai-common.yaml#
18 - A Synopsys DesignWare HDMI Controller IP
19 - A TOP control block controlling the Clocks and PHY
20 - A custom HDMI PHY in order to convert video to TMDS signal
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H A Dallwinner,sun8i-a83t-dw-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A83t DWC HDMI TX Encoder
10 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller
14 These DT bindings follow the Synopsys DWC HDMI TX bindings defined
15 in bridge/synopsys,dw-hdmi.yaml with the following device-specific
19 - Chen-Yu Tsai <wens@csie.org>
20 - Maxime Ripard <mripard@kernel.org>
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/openbmc/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip DWC HDMI TX Encoder
10 - Mark Yao <markyao0591@gmail.com>
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
22 - rockchip,rk3228-dw-hdmi
23 - rockchip,rk3288-dw-hdmi
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/openbmc/linux/drivers/gpu/drm/ingenic/
H A Dingenic-dw-hdmi.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
5 * Derived from dw_hdmi-imx.c with i.MX portions removed.
47 ingenic_dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, in ingenic_dw_hdmi_mode_valid() argument
51 if (mode->clock < 13500) in ingenic_dw_hdmi_mode_valid()
54 if (mode->clock > 216000) in ingenic_dw_hdmi_mode_valid()
69 { .compatible = "ingenic,jz4780-dw-hdmi" },
76 struct dw_hdmi *hdmi = (struct dw_hdmi *)data; in ingenic_dw_hdmi_cleanup() local
78 dw_hdmi_remove(hdmi); in ingenic_dw_hdmi_cleanup()
83 struct dw_hdmi *hdmi; in ingenic_dw_hdmi_probe() local
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H A DKconfig18 If M is selected the module will be called ingenic-drm.
30 tristate "Ingenic specific support for Synopsys DW HDMI"
34 Choose this option to enable Synopsys DesignWare HDMI based driver.
35 If you want to enable HDMI on Ingenic JZ4780 based SoC, you should
/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Dingenic,jz4780-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/ingenic,jz4780-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic JZ4780 HDMI Transmitter
10 - H. Nikolaus Schaller <hns@goldelico.com>
13 The HDMI Transmitter in the Ingenic JZ4780 is a Synopsys DesignWare HDMI 1.4
17 - $ref: synopsys,dw-hdmi.yaml#
21 const: ingenic,jz4780-dw-hdmi
23 reg-io-width:
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H A Drenesas,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/renesas,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car DWC HDMI TX Encoder
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
17 - $ref: synopsys,dw-hdmi.yaml#
22 - enum:
23 - renesas,r8a774a1-hdmi # for RZ/G2M compatible HDMI TX
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H A Dsynopsys,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Synopsys DesignWare HDMI TX Controller
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 This document defines device tree properties for the Synopsys DesignWare HDMI
14 TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
16 bindings for the platform-specific integrations of the DWC HDMI TX.
26 reg-io-width:
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/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
32 #define DRIVER_NAME "meson-dw-hdmi"
33 #define DRIVER_DESC "Amlogic Meson HDMI-TX DRM driver"
36 * DOC: HDMI Output
38 * HDMI Output is composed of :
40 * - A Synopsys DesignWare HDMI Controller IP
41 * - A TOP control block controlling the Clocks and PHY
42 * - A custom HDMI PHY in order convert video to TMDS signal
47 * | HDMI TOP |<= HPD
50 * | Synopsys HDMI | HDMI PHY |=> TMDS
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/openbmc/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_dw_hdmi.c1 // SPDX-License-Identifier: GPL-2.0+
22 struct sun8i_dw_hdmi *hdmi = encoder_to_sun8i_dw_hdmi(encoder); in sun8i_dw_hdmi_encoder_mode_set() local
24 clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000); in sun8i_dw_hdmi_encoder_mode_set()
33 sun8i_dw_hdmi_mode_valid_a83t(struct dw_hdmi *hdmi, void *data, in sun8i_dw_hdmi_mode_valid_a83t() argument
37 if (mode->clock > 297000) in sun8i_dw_hdmi_mode_valid_a83t()
44 sun8i_dw_hdmi_mode_valid_h6(struct dw_hdmi *hdmi, void *data, in sun8i_dw_hdmi_mode_valid_h6() argument
52 if (mode->clock > 594000) in sun8i_dw_hdmi_mode_valid_h6()
70 remote = of_graph_get_remote_node(node, 0, -1); in sun8i_dw_hdmi_find_possible_crtcs()
104 struct sun8i_dw_hdmi *hdmi; in sun8i_dw_hdmi_bind() local
107 if (!pdev->dev.of_node) in sun8i_dw_hdmi_bind()
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/openbmc/linux/drivers/gpu/drm/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
59 bool "Rockchip specific extensions for Synopsys DW HDMI"
62 for the Synopsys DesignWare HDMI driver. If you want to
63 enable HDMI on RK3288 or RK3399 based SoC, you should select
67 bool "Rockchip specific extensions for Synopsys DW MIPI DSI"
76 bool "Rockchip specific extensions for Innosilicon HDMI"
79 for the Innosilicon HDMI driver. If you want to enable
80 HDMI on RK3036 based SoC, you should select this option.
103 bool "Rockchip specific extensions for RK3066 HDMI"
107 for the RK3066 HDMI driver. If you want to enable
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H A Ddw_hdmi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
39 /* need to be unset if hdmi or i2c should control voltage */
61 * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
63 * @lcdsel_big: reg value of selecting vop big for HDMI
64 * @lcdsel_lit: reg value of selecting vop little for HDMI
80 struct dw_hdmi *hdmi; member
210 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) in rockchip_hdmi_parse_dt() argument
212 struct device_node *np = hdmi->dev->of_node; in rockchip_hdmi_parse_dt()
214 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in rockchip_hdmi_parse_dt()
215 if (IS_ERR(hdmi->regmap)) { in rockchip_hdmi_parse_dt()
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/openbmc/linux/arch/arc/boot/dts/
H A Daxs10x_mb.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
18 interrupt-parent = <&mb_intc>;
20 creg_rst: reset-controller@11220 {
21 compatible = "snps,axs10x-reset";
22 #reset-cells = <1>;
27 compatible = "snps,axs10x-i2s-pll-clock";
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/openbmc/u-boot/drivers/video/meson/
H A Dmeson_dw_hdmi.c1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
13 #include <dm/device-internal.h>
14 #include <dm/uclass-internal.h>
43 struct dw_hdmi hdmi; member
56 enum hdmi_compatible compat = dev_get_driver_data(priv->dev); in meson_hdmi_is_compatible()
61 static unsigned int dw_hdmi_top_read(struct dw_hdmi *hdmi, unsigned int addr) in dw_hdmi_top_read() argument
66 writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_read()
67 writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_read()
70 data = readl(hdmi->ioaddr + HDMITX_TOP_DATA_REG); in dw_hdmi_top_read()
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-inno-hdmi.txt1 ROCKCHIP HDMI PHY WITH INNO IP BLOCK
4 - compatible : should be one of the listed compatibles:
5 * "rockchip,rk3228-hdmi-phy",
6 * "rockchip,rk3328-hdmi-phy";
7 - reg : Address and length of the hdmi phy control register set
8 - clocks : phandle + clock specifier for the phy clocks
9 - clock-names : string, clock name, must contain "sysclk" for system
10 control and register configuration, "refoclk" for crystal-
11 oscillator reference PLL clock input and "refpclk" for pclk-
13 - #clock-cells: should be 0.
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/openbmc/linux/Documentation/gpu/bridge/
H A Ddw-hdmi.rst2 drm/bridge/dw-hdmi Synopsys DesignWare HDMI Controller
5 Synopsys DesignWare HDMI Controller
8 This section covers everything related to the Synopsys DesignWare HDMI
12 -------------------------------------
14 .. kernel-doc:: include/drm/bridge/dw_hdmi.h
/openbmc/u-boot/drivers/video/rockchip/
H A Drk3399_hdmi.c1 // SPDX-License-Identifier: GPL-2.0+
27 int vop_id = uc_plat->source_id; in rk3399_hdmi_enable()
28 struct rk3399_grf_regs *grf = priv->grf; in rk3399_hdmi_enable()
30 /* select the hdmi encoder input data from our source_id */ in rk3399_hdmi_enable()
31 rk_clrsetreg(&grf->soc_con20, GRF_RK3399_HDMI_VOP_SEL_MASK, in rk3399_hdmi_enable()
34 return dw_hdmi_enable(&priv->hdmi, edid); in rk3399_hdmi_enable()
40 struct dw_hdmi *hdmi = &priv->hdmi; in rk3399_hdmi_ofdata_to_platdata() local
42 hdmi->i2c_clk_high = 0x7a; in rk3399_hdmi_ofdata_to_platdata()
43 hdmi->i2c_clk_low = 0x8d; in rk3399_hdmi_ofdata_to_platdata()
55 /* Enable regulators required for HDMI */ in rk3399_hdmi_probe()
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/openbmc/u-boot/arch/arc/dts/
H A Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0+
5 /dts-v1/;
8 #include "dt-bindings/clock/snps,hsdk-cgu.h"
13 #address-cells = <1>;
14 #size-cells = <1>;
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <500000000>;
26 u-boot,dm-pre-reloc;
30 clk-fmeas {
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/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5260-xyref5260.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
27 stdout-path = "serial2:115200n8";
31 compatible = "fixed-clock";
32 clock-frequency = <24000000>;
33 clock-output-names = "fin_pll";
34 #clock-cells = <0>;
37 ioclk_pcm: clock-pcm-ext {
38 compatible = "fixed-clock";
39 clock-frequency = <2048000>;
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H A Dexynos5250-snow-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/sound/samsung-i2s.h>
30 stdout-path = "serial3:115200n8";
33 gpio-keys {
34 compatible = "gpio-keys";
35 pinctrl-names = "default";
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