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/openbmc/linux/Documentation/devicetree/bindings/display/exynos/
H A Dexynos_dp.txt6 -dptx-phy node(defined inside dp-controller node)
8 For the DP-PHY initialization, we use the dptx-phy node.
9 Required properties for dptx-phy: deprecated, use phys and phy-names
/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training_dpia.c69 DPIA_TS_UFP_DONE = 0xff /* Done training DPTX-to-DPIA hop. */
280 * - CR for the first hop (DPTX-to-DPIA) is assumed to be successful.
317 /* DPTX-to-DPIA */ in dpia_training_cr_non_transparent()
604 * - EQ for the first hop (DPTX-to-DPIA) is assumed to be successful.
642 /* DPTX-to-DPIA equalization always successful. */ in dpia_training_eq_non_transparent()
891 * (DPTX-to-DPIA) and last hop (DPRX).
909 if (hop == repeater_cnt) { /* DPTX-to-DPIA */ in dpia_training_end()
911 * DPTX-to-DPIA hop trained. No DPCD write needed for first hop. in dpia_training_end()
1013 /* Train each hop in turn starting with the one closest to DPTX. in dpia_perform_link_training()
H A Dlink_dp_dpia_bw.c325 /* Send request acknowledgment to Turn ON DPTX support */ in link_dp_dpia_set_dptx_usb4_bw_alloc_support()
334 DC_LOG_DEBUG("%s: FAILURE Enabling DPtx BW Allocation Mode Support for link(%d)\n", in link_dp_dpia_set_dptx_usb4_bw_alloc_support()
337 // SUCCESS Enabled DPtx BW Allocation Mode Support in link_dp_dpia_set_dptx_usb4_bw_alloc_support()
338 DC_LOG_DEBUG("%s: SUCCESS Enabling DPtx BW Allocation Mode Support for link(%d)\n", in link_dp_dpia_set_dptx_usb4_bw_alloc_support()
H A Dlink_dp_training.c915 * AUX_RD_INTERVAL for DPTX-to-DPIA hop. in configure_lttpr_mode_non_transparent()
1444 * If the upstream DPTX and downstream DPRX both support TPS4, in dp_transition_to_video_idle()
1507 * Per DP specs starting from here, DPTX device shall not issue in dp_perform_link_training()
/openbmc/linux/drivers/gpu/drm/rockchip/
H A Dcdn-dp-reg.h114 /* dptx phy addr */
123 /* dptx hpd addr */
151 /* dptx stream addr */
169 /* dptx glbl addr */
H A Dcdn-dp-core.c50 #define CDN_DP_FIRMWARE "rockchip/dptx.bin"
155 int dptx; in cdn_dp_get_port_lanes() local
158 dptx = extcon_get_state(edev, EXTCON_DISP_DP); in cdn_dp_get_port_lanes()
159 if (dptx > 0) { in cdn_dp_get_port_lanes()
761 dp->dptx_rst = devm_reset_control_get(dev, "dptx"); in cdn_dp_parse_dt()
/openbmc/linux/drivers/gpu/drm/bridge/analogix/
H A DMakefile2 analogix_dp-objs := analogix_dp_core.o analogix_dp_reg.o analogix-i2c-dptx.o
H A Danalogix-i2c-dptx.c14 #include "analogix-i2c-dptx.h"
H A Danalogix-anx78xx.h9 #include "analogix-i2c-dptx.h"
H A Danalogix-anx6345.c31 #include "analogix-i2c-dptx.h"
58 /* I2C Slave addresses of ANX6345 are mapped as DPTX and SYS */
/openbmc/linux/drivers/gpu/drm/mediatek/
H A DKconfig24 tristate "DRM DPTX Support for MediaTek SoCs"
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dmt8195-mt6359.yaml30 mediatek,dptx-codec:
/openbmc/linux/Documentation/devicetree/bindings/display/rockchip/
H A Dcdn-dp-rockchip.txt16 Required elements: "apb", "core", "dptx", "spdif"
/openbmc/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,dp.yaml92 dptx@1c600000 {
/openbmc/linux/sound/soc/mediatek/mt8188/
H A Dmt8188-dai-etdm.c367 else if (!strncmp(name, "DPTX", strlen("DPTX"))) in get_etdm_id_by_name()
1344 {"DPTX", NULL, "DPTX_MCLK"},
1383 {"DPTX", NULL, "ETDM3_OUT_CG"},
1407 {"DPTX", NULL, "ETDM3_OUT_EN"},
1408 {"DPTX", NULL, "DPTX_EN"},
1667 {"DPTX", NULL, "DPTX_OUT_MUX"},
1669 {"ETDM_OUTPUT", NULL, "DPTX"},
2431 /* dptx configure */ in mtk_dai_hdmitx_dptx_hw_params()
2500 .name = "DPTX",
2503 .stream_name = "DPTX",
H A Dmt8188-mt6359.c136 SND_SOC_DAILINK_DEFS(dptx,
137 DAILINK_COMP_ARRAY(COMP_CPU("DPTX")),
940 SND_SOC_DAILINK_REG(dptx),
/openbmc/u-boot/drivers/misc/
H A Daspeed_dp.c104 /* reset for DPTX and DPMCU if MCU isn't running */ in aspeed_dp_probe()
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dphy-cadence-torrent.yaml51 - description: Offset of the DPTX PHY configuration registers.
/openbmc/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-dai-etdm.c1306 {"DPTX Playback", NULL, "DPTX_OUT_MUX"},
1308 {"ETDM_OUTPUT", NULL, "DPTX Playback"},
2369 /* dptx configure */ in mtk_dai_hdmitx_dptx_hw_params()
2412 /* enable dptx interface */ in mtk_dai_hdmitx_dptx_trigger()
2426 /* disable dptx interface */ in mtk_dai_hdmitx_dptx_trigger()
2521 .name = "DPTX",
2524 .stream_name = "DPTX Playback",
H A Dmt8195-mt6359.c926 DAILINK_COMP_ARRAY(COMP_CPU("DPTX")),
1461 dp_node = of_parse_phandle(pdev->dev.of_node, "mediatek,dptx-codec", 0); in mt8195_mt6359_dev_probe()
1475 dev_dbg(&pdev->dev, "No property 'dptx-codec'\n"); in mt8195_mt6359_dev_probe()
/openbmc/u-boot/board/kosagi/novena/
H A Dvideo.c157 * DPTX in it6251_program_regs()
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynosautov9.c501 /* DPTX */
671 /* DPTX */
828 /* DPTX */
/openbmc/openbmc/poky/meta/recipes-kernel/linux-firmware/
H A Dlinux-firmware_20241210.bb431 ${PN}-rockchip-license ${PN}-rockchip-dptx \
1626 LICENSE:${PN}-rockchip-dptx = "Firmware-rockchip"
1628 FILES:${PN}-rockchip-dptx = "${nonarch_base_libdir}/firmware/rockchip/dptx.bin*"
1629 RDEPENDS:${PN}-rockchip-dptx = "${PN}-rockchip-license"
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_dp_link_training.c247 * The DPTX shall read the DPRX caps after LTTPR detection, so re-read in intel_dp_init_lttpr_and_dprx_caps()
765 * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate in intel_dp_prepare_link_train()
/openbmc/linux/drivers/phy/cadence/
H A Dphy-cadence-torrent.c62 * register offsets from DPTX PHY register block base (i.e MHDP
350 void __iomem *base; /* DPTX registers base */
607 /* DPTX mmr access functions */
2206 dev_err(dev, "Failed to init DPTX PHY regmap\n"); in cdns_torrent_dp_regmap_init()
2913 /* DPTX registers */ in cdns_torrent_phy_probe()

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