1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2f2e4d6a5SMarek Vasut /*
3f2e4d6a5SMarek Vasut * Novena video output support
4f2e4d6a5SMarek Vasut *
5331ae846SMarek Vasut * IT6251 code based on code Copyright (C) 2014 Sean Cross
6331ae846SMarek Vasut * from https://github.com/xobs/novena-linux.git commit
7331ae846SMarek Vasut * 3d85836ee1377d445531928361809612aa0a18db
8331ae846SMarek Vasut *
9f2e4d6a5SMarek Vasut * Copyright (C) 2014 Marek Vasut <marex@denx.de>
10f2e4d6a5SMarek Vasut */
11f2e4d6a5SMarek Vasut
12f2e4d6a5SMarek Vasut #include <common.h>
131221ce45SMasahiro Yamada #include <linux/errno.h>
14f2e4d6a5SMarek Vasut #include <asm/gpio.h>
15f2e4d6a5SMarek Vasut #include <asm/io.h>
16f2e4d6a5SMarek Vasut #include <asm/arch/clock.h>
17f2e4d6a5SMarek Vasut #include <asm/arch/crm_regs.h>
18f2e4d6a5SMarek Vasut #include <asm/arch/imx-regs.h>
19f2e4d6a5SMarek Vasut #include <asm/arch/iomux.h>
20f2e4d6a5SMarek Vasut #include <asm/arch/mxc_hdmi.h>
21f2e4d6a5SMarek Vasut #include <asm/arch/sys_proto.h>
22552a848eSStefano Babic #include <asm/mach-imx/iomux-v3.h>
23552a848eSStefano Babic #include <asm/mach-imx/mxc_i2c.h>
24552a848eSStefano Babic #include <asm/mach-imx/video.h>
25f2e4d6a5SMarek Vasut #include <i2c.h>
26f2e4d6a5SMarek Vasut #include <input.h>
27f2e4d6a5SMarek Vasut #include <ipu_pixfmt.h>
28f2e4d6a5SMarek Vasut #include <linux/fb.h>
29f2e4d6a5SMarek Vasut #include <linux/input.h>
30f2e4d6a5SMarek Vasut #include <malloc.h>
31f2e4d6a5SMarek Vasut #include <stdio_dev.h>
32f2e4d6a5SMarek Vasut
33f2e4d6a5SMarek Vasut #include "novena.h"
34f2e4d6a5SMarek Vasut
35331ae846SMarek Vasut #define IT6251_VENDOR_ID_LOW 0x00
36331ae846SMarek Vasut #define IT6251_VENDOR_ID_HIGH 0x01
37331ae846SMarek Vasut #define IT6251_DEVICE_ID_LOW 0x02
38331ae846SMarek Vasut #define IT6251_DEVICE_ID_HIGH 0x03
39331ae846SMarek Vasut #define IT6251_SYSTEM_STATUS 0x0d
40331ae846SMarek Vasut #define IT6251_SYSTEM_STATUS_RINTSTATUS (1 << 0)
41331ae846SMarek Vasut #define IT6251_SYSTEM_STATUS_RHPDSTATUS (1 << 1)
42331ae846SMarek Vasut #define IT6251_SYSTEM_STATUS_RVIDEOSTABLE (1 << 2)
43331ae846SMarek Vasut #define IT6251_SYSTEM_STATUS_RPLL_IOLOCK (1 << 3)
44331ae846SMarek Vasut #define IT6251_SYSTEM_STATUS_RPLL_XPLOCK (1 << 4)
45331ae846SMarek Vasut #define IT6251_SYSTEM_STATUS_RPLL_SPLOCK (1 << 5)
46331ae846SMarek Vasut #define IT6251_SYSTEM_STATUS_RAUXFREQ_LOCK (1 << 6)
47331ae846SMarek Vasut #define IT6251_REF_STATE 0x0e
48331ae846SMarek Vasut #define IT6251_REF_STATE_MAIN_LINK_DISABLED (1 << 0)
49331ae846SMarek Vasut #define IT6251_REF_STATE_AUX_CHANNEL_READ (1 << 1)
50331ae846SMarek Vasut #define IT6251_REF_STATE_CR_PATTERN (1 << 2)
51331ae846SMarek Vasut #define IT6251_REF_STATE_EQ_PATTERN (1 << 3)
52331ae846SMarek Vasut #define IT6251_REF_STATE_NORMAL_OPERATION (1 << 4)
53331ae846SMarek Vasut #define IT6251_REF_STATE_MUTED (1 << 5)
54331ae846SMarek Vasut
55331ae846SMarek Vasut #define IT6251_REG_PCLK_CNT_LOW 0x57
56331ae846SMarek Vasut #define IT6251_REG_PCLK_CNT_HIGH 0x58
57331ae846SMarek Vasut
58331ae846SMarek Vasut #define IT6521_RETRY_MAX 20
59331ae846SMarek Vasut
it6251_is_stable(void)60331ae846SMarek Vasut static int it6251_is_stable(void)
61331ae846SMarek Vasut {
62331ae846SMarek Vasut const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
63331ae846SMarek Vasut const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
64331ae846SMarek Vasut int status;
65331ae846SMarek Vasut int clkcnt;
66331ae846SMarek Vasut int rpclkcnt;
67331ae846SMarek Vasut int refstate;
68331ae846SMarek Vasut
69331ae846SMarek Vasut rpclkcnt = (i2c_reg_read(caddr, 0x13) & 0xff) |
70331ae846SMarek Vasut ((i2c_reg_read(caddr, 0x14) << 8) & 0x0f00);
71331ae846SMarek Vasut debug("RPCLKCnt: %d\n", rpclkcnt);
72331ae846SMarek Vasut
73331ae846SMarek Vasut status = i2c_reg_read(caddr, IT6251_SYSTEM_STATUS);
74331ae846SMarek Vasut debug("System status: 0x%02x\n", status);
75331ae846SMarek Vasut
76331ae846SMarek Vasut clkcnt = (i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_LOW) & 0xff) |
77331ae846SMarek Vasut ((i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_HIGH) << 8) &
78331ae846SMarek Vasut 0x0f00);
79331ae846SMarek Vasut debug("Clock: 0x%02x\n", clkcnt);
80331ae846SMarek Vasut
81331ae846SMarek Vasut refstate = i2c_reg_read(laddr, IT6251_REF_STATE);
82331ae846SMarek Vasut debug("Ref Link State: 0x%02x\n", refstate);
83331ae846SMarek Vasut
84331ae846SMarek Vasut if ((refstate & 0x1f) != 0)
85331ae846SMarek Vasut return 0;
86331ae846SMarek Vasut
87331ae846SMarek Vasut /* If video is muted, that's a failure */
88331ae846SMarek Vasut if (refstate & IT6251_REF_STATE_MUTED)
89331ae846SMarek Vasut return 0;
90331ae846SMarek Vasut
91331ae846SMarek Vasut if (!(status & IT6251_SYSTEM_STATUS_RVIDEOSTABLE))
92331ae846SMarek Vasut return 0;
93331ae846SMarek Vasut
94331ae846SMarek Vasut return 1;
95331ae846SMarek Vasut }
96331ae846SMarek Vasut
it6251_ready(void)97331ae846SMarek Vasut static int it6251_ready(void)
98331ae846SMarek Vasut {
99331ae846SMarek Vasut const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
100331ae846SMarek Vasut
101331ae846SMarek Vasut /* Test if the IT6251 came out of reset by reading ID regs. */
102331ae846SMarek Vasut if (i2c_reg_read(caddr, IT6251_VENDOR_ID_LOW) != 0x15)
103331ae846SMarek Vasut return 0;
104331ae846SMarek Vasut if (i2c_reg_read(caddr, IT6251_VENDOR_ID_HIGH) != 0xca)
105331ae846SMarek Vasut return 0;
106331ae846SMarek Vasut if (i2c_reg_read(caddr, IT6251_DEVICE_ID_LOW) != 0x51)
107331ae846SMarek Vasut return 0;
108331ae846SMarek Vasut if (i2c_reg_read(caddr, IT6251_DEVICE_ID_HIGH) != 0x62)
109331ae846SMarek Vasut return 0;
110331ae846SMarek Vasut
111331ae846SMarek Vasut return 1;
112331ae846SMarek Vasut }
113331ae846SMarek Vasut
it6251_program_regs(void)114331ae846SMarek Vasut static void it6251_program_regs(void)
115331ae846SMarek Vasut {
116331ae846SMarek Vasut const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
117331ae846SMarek Vasut const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
118331ae846SMarek Vasut
119331ae846SMarek Vasut i2c_reg_write(caddr, 0x05, 0x00);
120331ae846SMarek Vasut mdelay(1);
121331ae846SMarek Vasut
122331ae846SMarek Vasut /* set LVDSRX address, and enable */
123331ae846SMarek Vasut i2c_reg_write(caddr, 0xfd, 0xbc);
124331ae846SMarek Vasut i2c_reg_write(caddr, 0xfe, 0x01);
125331ae846SMarek Vasut
126331ae846SMarek Vasut /*
127331ae846SMarek Vasut * LVDSRX
128331ae846SMarek Vasut */
129331ae846SMarek Vasut /* This write always fails, because the chip goes into reset */
130331ae846SMarek Vasut /* reset LVDSRX */
131331ae846SMarek Vasut i2c_reg_write(laddr, 0x05, 0xff);
132331ae846SMarek Vasut i2c_reg_write(laddr, 0x05, 0x00);
133331ae846SMarek Vasut
134331ae846SMarek Vasut /* reset LVDSRX PLL */
135331ae846SMarek Vasut i2c_reg_write(laddr, 0x3b, 0x42);
136331ae846SMarek Vasut i2c_reg_write(laddr, 0x3b, 0x43);
137331ae846SMarek Vasut
138331ae846SMarek Vasut /* something with SSC PLL */
139331ae846SMarek Vasut i2c_reg_write(laddr, 0x3c, 0x08);
140331ae846SMarek Vasut /* don't swap links, but writing reserved registers */
141331ae846SMarek Vasut i2c_reg_write(laddr, 0x0b, 0x88);
142331ae846SMarek Vasut
143331ae846SMarek Vasut /* JEIDA, 8-bit depth 0x11, orig 0x42 */
144331ae846SMarek Vasut i2c_reg_write(laddr, 0x2c, 0x01);
145331ae846SMarek Vasut /* "reserved" */
146331ae846SMarek Vasut i2c_reg_write(laddr, 0x32, 0x04);
147331ae846SMarek Vasut /* "reserved" */
148331ae846SMarek Vasut i2c_reg_write(laddr, 0x35, 0xe0);
149331ae846SMarek Vasut /* "reserved" + clock delay */
150331ae846SMarek Vasut i2c_reg_write(laddr, 0x2b, 0x24);
151331ae846SMarek Vasut
152331ae846SMarek Vasut /* reset LVDSRX pix clock */
153331ae846SMarek Vasut i2c_reg_write(laddr, 0x05, 0x02);
154331ae846SMarek Vasut i2c_reg_write(laddr, 0x05, 0x00);
155331ae846SMarek Vasut
156331ae846SMarek Vasut /*
157331ae846SMarek Vasut * DPTX
158331ae846SMarek Vasut */
159331ae846SMarek Vasut /* set for two lane mode, normal op, no swapping, no downspread */
160331ae846SMarek Vasut i2c_reg_write(caddr, 0x16, 0x02);
161331ae846SMarek Vasut
162331ae846SMarek Vasut /* some AUX channel EDID magic */
163331ae846SMarek Vasut i2c_reg_write(caddr, 0x23, 0x40);
164331ae846SMarek Vasut
165331ae846SMarek Vasut /* power down lanes 3-0 */
166331ae846SMarek Vasut i2c_reg_write(caddr, 0x5c, 0xf3);
167331ae846SMarek Vasut
168331ae846SMarek Vasut /* enable DP scrambling, change EQ CR phase */
169331ae846SMarek Vasut i2c_reg_write(caddr, 0x5f, 0x06);
170331ae846SMarek Vasut
171331ae846SMarek Vasut /* color mode RGB, pclk/2 */
172331ae846SMarek Vasut i2c_reg_write(caddr, 0x60, 0x02);
173331ae846SMarek Vasut /* dual pixel input mode, no EO swap, no RGB swap */
174331ae846SMarek Vasut i2c_reg_write(caddr, 0x61, 0x04);
175331ae846SMarek Vasut /* M444B24 video format */
176331ae846SMarek Vasut i2c_reg_write(caddr, 0x62, 0x01);
177331ae846SMarek Vasut
178331ae846SMarek Vasut /* vesa range / not interlace / vsync high / hsync high */
179331ae846SMarek Vasut i2c_reg_write(caddr, 0xa0, 0x0F);
180331ae846SMarek Vasut
181331ae846SMarek Vasut /* hpd event timer set to 1.6-ish ms */
182331ae846SMarek Vasut i2c_reg_write(caddr, 0xc9, 0xf5);
183331ae846SMarek Vasut
184331ae846SMarek Vasut /* more reserved magic */
185331ae846SMarek Vasut i2c_reg_write(caddr, 0xca, 0x4d);
186331ae846SMarek Vasut i2c_reg_write(caddr, 0xcb, 0x37);
187331ae846SMarek Vasut
188331ae846SMarek Vasut /* enhanced framing mode, auto video fifo reset, video mute disable */
189331ae846SMarek Vasut i2c_reg_write(caddr, 0xd3, 0x03);
190331ae846SMarek Vasut
191331ae846SMarek Vasut /* "vidstmp" and some reserved stuff */
192331ae846SMarek Vasut i2c_reg_write(caddr, 0xd4, 0x45);
193331ae846SMarek Vasut
194331ae846SMarek Vasut /* queue number -- reserved */
195331ae846SMarek Vasut i2c_reg_write(caddr, 0xe7, 0xa0);
196331ae846SMarek Vasut /* info frame packets and reserved */
197331ae846SMarek Vasut i2c_reg_write(caddr, 0xe8, 0x33);
198331ae846SMarek Vasut /* more AVI stuff */
199331ae846SMarek Vasut i2c_reg_write(caddr, 0xec, 0x00);
200331ae846SMarek Vasut
201331ae846SMarek Vasut /* select PC master reg for aux channel? */
202331ae846SMarek Vasut i2c_reg_write(caddr, 0x23, 0x42);
203331ae846SMarek Vasut
204331ae846SMarek Vasut /* send PC request commands */
205331ae846SMarek Vasut i2c_reg_write(caddr, 0x24, 0x00);
206331ae846SMarek Vasut i2c_reg_write(caddr, 0x25, 0x00);
207331ae846SMarek Vasut i2c_reg_write(caddr, 0x26, 0x00);
208331ae846SMarek Vasut
209331ae846SMarek Vasut /* native aux read */
210331ae846SMarek Vasut i2c_reg_write(caddr, 0x2b, 0x00);
211331ae846SMarek Vasut /* back to internal */
212331ae846SMarek Vasut i2c_reg_write(caddr, 0x23, 0x40);
213331ae846SMarek Vasut
214331ae846SMarek Vasut /* voltage swing level 3 */
215331ae846SMarek Vasut i2c_reg_write(caddr, 0x19, 0xff);
216331ae846SMarek Vasut /* pre-emphasis level 3 */
217331ae846SMarek Vasut i2c_reg_write(caddr, 0x1a, 0xff);
218331ae846SMarek Vasut
219331ae846SMarek Vasut /* start link training */
220331ae846SMarek Vasut i2c_reg_write(caddr, 0x17, 0x01);
221331ae846SMarek Vasut }
222331ae846SMarek Vasut
it6251_init(void)223331ae846SMarek Vasut static int it6251_init(void)
224331ae846SMarek Vasut {
225331ae846SMarek Vasut const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
226331ae846SMarek Vasut int reg;
227331ae846SMarek Vasut int tries, retries = 0;
228331ae846SMarek Vasut
229331ae846SMarek Vasut for (retries = 0; retries < IT6521_RETRY_MAX; retries++) {
230331ae846SMarek Vasut /* Program the chip. */
231331ae846SMarek Vasut it6251_program_regs();
232331ae846SMarek Vasut
233331ae846SMarek Vasut /* Wait for video stable. */
234331ae846SMarek Vasut for (tries = 0; tries < 100; tries++) {
235331ae846SMarek Vasut reg = i2c_reg_read(caddr, 0x17);
236331ae846SMarek Vasut /* Test Link CFG, STS, LCS read done. */
237331ae846SMarek Vasut if ((reg & 0xe0) != 0xe0) {
238331ae846SMarek Vasut /* Not yet, wait a bit more. */
239331ae846SMarek Vasut mdelay(2);
240331ae846SMarek Vasut continue;
241331ae846SMarek Vasut }
242331ae846SMarek Vasut
243331ae846SMarek Vasut /* Test if the video input is stable. */
244331ae846SMarek Vasut if (it6251_is_stable())
245331ae846SMarek Vasut return 0;
246331ae846SMarek Vasut }
247331ae846SMarek Vasut /*
248331ae846SMarek Vasut * If we couldn't stabilize, requeue and try again,
249331ae846SMarek Vasut * because it means that the LVDS channel isn't
250331ae846SMarek Vasut * stable yet.
251331ae846SMarek Vasut */
252331ae846SMarek Vasut printf("Display didn't stabilize.\n");
253331ae846SMarek Vasut printf("This may be because the LVDS port is still in powersave mode.\n");
254331ae846SMarek Vasut mdelay(50);
255331ae846SMarek Vasut }
256331ae846SMarek Vasut
257331ae846SMarek Vasut return -EINVAL;
258331ae846SMarek Vasut }
259331ae846SMarek Vasut
enable_hdmi(struct display_info_t const * dev)260f2e4d6a5SMarek Vasut static void enable_hdmi(struct display_info_t const *dev)
261f2e4d6a5SMarek Vasut {
262f2e4d6a5SMarek Vasut imx_enable_hdmi_phy();
263f2e4d6a5SMarek Vasut }
264f2e4d6a5SMarek Vasut
265331ae846SMarek Vasut static int lvds_enabled;
266331ae846SMarek Vasut
enable_lvds(struct display_info_t const * dev)267331ae846SMarek Vasut static void enable_lvds(struct display_info_t const *dev)
268331ae846SMarek Vasut {
269331ae846SMarek Vasut if (lvds_enabled)
270331ae846SMarek Vasut return;
271331ae846SMarek Vasut
272331ae846SMarek Vasut /* ITE IT6251 power enable. */
273331ae846SMarek Vasut gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 0);
274331ae846SMarek Vasut mdelay(10);
275331ae846SMarek Vasut gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 1);
276331ae846SMarek Vasut mdelay(20);
277331ae846SMarek Vasut lvds_enabled = 1;
278331ae846SMarek Vasut }
279331ae846SMarek Vasut
detect_lvds(struct display_info_t const * dev)280331ae846SMarek Vasut static int detect_lvds(struct display_info_t const *dev)
281331ae846SMarek Vasut {
282331ae846SMarek Vasut int ret, loops = 250;
283331ae846SMarek Vasut
284331ae846SMarek Vasut enable_lvds(dev);
285331ae846SMarek Vasut
286331ae846SMarek Vasut ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
287331ae846SMarek Vasut if (ret) {
288331ae846SMarek Vasut puts("Cannot select IT6251 I2C bus.\n");
289331ae846SMarek Vasut return 0;
290331ae846SMarek Vasut }
291331ae846SMarek Vasut
292331ae846SMarek Vasut /* Wait up-to ~250 mS for the LVDS to come up. */
293331ae846SMarek Vasut while (--loops) {
294331ae846SMarek Vasut ret = it6251_ready();
295331ae846SMarek Vasut if (ret)
296331ae846SMarek Vasut return ret;
297331ae846SMarek Vasut
298331ae846SMarek Vasut mdelay(1);
299331ae846SMarek Vasut }
300331ae846SMarek Vasut
301331ae846SMarek Vasut return 0;
302331ae846SMarek Vasut }
303331ae846SMarek Vasut
304f2e4d6a5SMarek Vasut struct display_info_t const displays[] = {
305f2e4d6a5SMarek Vasut {
306f2e4d6a5SMarek Vasut /* HDMI Output */
307f2e4d6a5SMarek Vasut .bus = -1,
308f2e4d6a5SMarek Vasut .addr = 0,
309f2e4d6a5SMarek Vasut .pixfmt = IPU_PIX_FMT_RGB24,
310f2e4d6a5SMarek Vasut .detect = detect_hdmi,
311f2e4d6a5SMarek Vasut .enable = enable_hdmi,
312f2e4d6a5SMarek Vasut .mode = {
313f2e4d6a5SMarek Vasut .name = "HDMI",
314f2e4d6a5SMarek Vasut .refresh = 60,
315f2e4d6a5SMarek Vasut .xres = 1024,
316f2e4d6a5SMarek Vasut .yres = 768,
317f2e4d6a5SMarek Vasut .pixclock = 15384,
318f2e4d6a5SMarek Vasut .left_margin = 220,
319f2e4d6a5SMarek Vasut .right_margin = 40,
320f2e4d6a5SMarek Vasut .upper_margin = 21,
321f2e4d6a5SMarek Vasut .lower_margin = 7,
322f2e4d6a5SMarek Vasut .hsync_len = 60,
323f2e4d6a5SMarek Vasut .vsync_len = 10,
324f2e4d6a5SMarek Vasut .sync = FB_SYNC_EXT,
325f2e4d6a5SMarek Vasut .vmode = FB_VMODE_NONINTERLACED
326f2e4d6a5SMarek Vasut },
327331ae846SMarek Vasut }, {
328331ae846SMarek Vasut /* LVDS Output: N133HSE-EA1 Rev. C1 */
329331ae846SMarek Vasut .bus = -1,
330331ae846SMarek Vasut .pixfmt = IPU_PIX_FMT_RGB24,
331331ae846SMarek Vasut .detect = detect_lvds,
332331ae846SMarek Vasut .enable = enable_lvds,
333331ae846SMarek Vasut .mode = {
334331ae846SMarek Vasut .name = "Chimei-FHD",
335331ae846SMarek Vasut .refresh = 60,
336331ae846SMarek Vasut .xres = 1920,
337331ae846SMarek Vasut .yres = 1080,
338331ae846SMarek Vasut .pixclock = 15384,
339331ae846SMarek Vasut .left_margin = 148,
340331ae846SMarek Vasut .right_margin = 88,
341331ae846SMarek Vasut .upper_margin = 36,
342331ae846SMarek Vasut .lower_margin = 4,
343331ae846SMarek Vasut .hsync_len = 44,
344331ae846SMarek Vasut .vsync_len = 5,
345331ae846SMarek Vasut .sync = FB_SYNC_HOR_HIGH_ACT |
346331ae846SMarek Vasut FB_SYNC_VERT_HIGH_ACT |
347331ae846SMarek Vasut FB_SYNC_EXT,
348331ae846SMarek Vasut .vmode = FB_VMODE_NONINTERLACED,
349331ae846SMarek Vasut },
350f2e4d6a5SMarek Vasut },
351f2e4d6a5SMarek Vasut };
352f2e4d6a5SMarek Vasut
353f2e4d6a5SMarek Vasut size_t display_count = ARRAY_SIZE(displays);
354f2e4d6a5SMarek Vasut
enable_vpll(void)355331ae846SMarek Vasut static void enable_vpll(void)
356331ae846SMarek Vasut {
357331ae846SMarek Vasut struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
358331ae846SMarek Vasut int timeout = 100000;
359331ae846SMarek Vasut
360331ae846SMarek Vasut setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
361331ae846SMarek Vasut
362331ae846SMarek Vasut clrsetbits_le32(&ccm->analog_pll_video,
363331ae846SMarek Vasut BM_ANADIG_PLL_VIDEO_DIV_SELECT |
364331ae846SMarek Vasut BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
365331ae846SMarek Vasut BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
366331ae846SMarek Vasut BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
367331ae846SMarek Vasut
368331ae846SMarek Vasut writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
369331ae846SMarek Vasut writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
370331ae846SMarek Vasut
371331ae846SMarek Vasut clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
372331ae846SMarek Vasut
373331ae846SMarek Vasut while (timeout--)
374331ae846SMarek Vasut if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
375331ae846SMarek Vasut break;
376331ae846SMarek Vasut if (timeout < 0)
377331ae846SMarek Vasut printf("Warning: video pll lock timeout!\n");
378331ae846SMarek Vasut
379331ae846SMarek Vasut clrsetbits_le32(&ccm->analog_pll_video,
380331ae846SMarek Vasut BM_ANADIG_PLL_VIDEO_BYPASS,
381331ae846SMarek Vasut BM_ANADIG_PLL_VIDEO_ENABLE);
382331ae846SMarek Vasut }
383331ae846SMarek Vasut
setup_display_clock(void)384f2e4d6a5SMarek Vasut void setup_display_clock(void)
385f2e4d6a5SMarek Vasut {
386f2e4d6a5SMarek Vasut struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
387f2e4d6a5SMarek Vasut struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
388f2e4d6a5SMarek Vasut
389f2e4d6a5SMarek Vasut enable_ipu_clock();
390331ae846SMarek Vasut enable_vpll();
391f2e4d6a5SMarek Vasut imx_setup_hdmi();
392f2e4d6a5SMarek Vasut
393331ae846SMarek Vasut /* Turn on IPU LDB DI0 clocks */
394f2e4d6a5SMarek Vasut setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
395f2e4d6a5SMarek Vasut
396331ae846SMarek Vasut /* Switch LDB DI0 to PLL5 (Video PLL) */
397f2e4d6a5SMarek Vasut clrsetbits_le32(&mxc_ccm->cs2cdr,
398331ae846SMarek Vasut MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
399331ae846SMarek Vasut (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
400f2e4d6a5SMarek Vasut
401331ae846SMarek Vasut /* LDB clock div by 3.5 */
402331ae846SMarek Vasut clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
403f2e4d6a5SMarek Vasut
404331ae846SMarek Vasut /* DI0 clock derived from ldb_di0_clk */
405331ae846SMarek Vasut clrsetbits_le32(&mxc_ccm->chsccdr,
406331ae846SMarek Vasut MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
407331ae846SMarek Vasut (CHSCCDR_CLK_SEL_LDB_DI0 <<
408331ae846SMarek Vasut MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
409331ae846SMarek Vasut );
410f2e4d6a5SMarek Vasut
411331ae846SMarek Vasut /* Enable both LVDS channels, both connected to DI0. */
412331ae846SMarek Vasut writel(IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH |
413331ae846SMarek Vasut IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA |
414331ae846SMarek Vasut IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
415331ae846SMarek Vasut IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA |
416331ae846SMarek Vasut IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
417331ae846SMarek Vasut IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
418331ae846SMarek Vasut IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 |
419f2e4d6a5SMarek Vasut IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
420f2e4d6a5SMarek Vasut &iomux->gpr[2]);
421f2e4d6a5SMarek Vasut
422331ae846SMarek Vasut clrsetbits_le32(&iomux->gpr[3],
423331ae846SMarek Vasut IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
424331ae846SMarek Vasut IOMUXC_GPR3_LVDS1_MUX_CTL_MASK,
425331ae846SMarek Vasut (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
426331ae846SMarek Vasut IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
427331ae846SMarek Vasut (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
428331ae846SMarek Vasut IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
429331ae846SMarek Vasut );
430331ae846SMarek Vasut }
431331ae846SMarek Vasut
setup_display_lvds(void)432331ae846SMarek Vasut void setup_display_lvds(void)
433331ae846SMarek Vasut {
434331ae846SMarek Vasut int ret;
435331ae846SMarek Vasut
436331ae846SMarek Vasut ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
437331ae846SMarek Vasut if (ret) {
438331ae846SMarek Vasut puts("Cannot select LVDS-to-eDP I2C bus.\n");
439331ae846SMarek Vasut return;
440331ae846SMarek Vasut }
441331ae846SMarek Vasut
442331ae846SMarek Vasut /* The IT6251 should be ready now, if it's not, it's not connected. */
443331ae846SMarek Vasut ret = it6251_ready();
444331ae846SMarek Vasut if (!ret)
445331ae846SMarek Vasut return;
446331ae846SMarek Vasut
447331ae846SMarek Vasut /* Init the LVDS-to-eDP chip and if it succeeded, enable backlight. */
448331ae846SMarek Vasut ret = it6251_init();
449331ae846SMarek Vasut if (!ret) {
450331ae846SMarek Vasut /* Backlight power enable. */
451331ae846SMarek Vasut gpio_direction_output(NOVENA_BACKLIGHT_PWR_GPIO, 1);
452331ae846SMarek Vasut /* PWM backlight pin, always on for full brightness. */
453331ae846SMarek Vasut gpio_direction_output(NOVENA_BACKLIGHT_PWM_GPIO, 1);
454331ae846SMarek Vasut }
455f2e4d6a5SMarek Vasut }
456