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Searched +full:dma +full:- +full:noncoherent (Results 1 – 23 of 23) sorted by relevance

/openbmc/linux/arch/arc/mm/
H A Ddma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 #include <linux/dma-map-ops.h>
11 * ARCH specific callbacks for generic noncoherent DMA ops
12 * - hardware IOC not available (or "dma-coherent" not set for device in DT)
13 * - But still handle both coherent and non-coherent requests from caller
15 * For DMA coherent hardware (IOC) generic code suffices
23 * Yeah this bit us - STAR 9000898266 in arch_dma_prep_coherent()
37 * dma-mapping: provide a generic dma-noncoherent implementation)"
40 * |----------------------------------------------------------------
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/openbmc/linux/arch/riscv/mm/
H A Dcache-ops.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <asm/dma-noncoherent.h>
H A Dpmem.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <asm/dma-noncoherent.h>
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
3 CFLAGS_init.o := -mcmodel=medany
5 CFLAGS_init.o += -fno-pie
15 obj-y += init.o
16 obj-$(CONFIG_MMU) += extable.o fault.o pageattr.o pgtable.o
17 obj-y += cacheflush.o
18 obj-y += context.o
19 obj-y += pmem.o
22 obj-$(CONFIG_SMP) += tlbflush.o
24 obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
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H A Ddma-noncoherent.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V specific functions to support DMA for non-coherent devices
8 #include <linux/dma-direct.h>
9 #include <linux/dma-map-ops.h>
12 #include <asm/dma-noncoherent.h>
136 "%s %s: ARCH_DMA_MINALIGN smaller than riscv,cbom-block-size (%d < %d)", in arch_setup_dma_ops()
141 "%s %s: device non-coherent but no non-coherent operations supported", in arch_setup_dma_ops()
144 dev->dma_coherent = coherent; in arch_setup_dma_ops()
150 "Non-coherent DMA support enabled without a block size\n"); in riscv_noncoherent_supported()
/openbmc/linux/arch/powerpc/mm/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the linux ppc-specific parts of the memory manager.
6 ccflags-$(CONFIG_PPC64) := $(NO_MINIMAL_TOC)
8 obj-y := fault.o mem.o pgtable.o maccess.o pageattr.o \
10 pgtable-frag.o ioremap.o ioremap_$(BITS).o \
11 init-common.o mmu_context.o drmem.o \
13 obj-$(CONFIG_PPC_MMU_NOHASH) += nohash/
14 obj-$(CONFIG_PPC_BOOK3S_32) += book3s32/
15 obj-$(CONFIG_PPC_BOOK3S_64) += book3s64/
16 obj-$(CONFIG_NUMA) += numa.o
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/openbmc/linux/arch/mips/mm/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the Linux/MIPS-specific parts of the memory manager.
6 obj-y += cache.o
7 obj-y += context.o
8 obj-y += extable.o
9 obj-y += fault.o
10 obj-y += init.o
11 obj-y += mmap.o
12 obj-y += page.o
13 obj-y += page-funcs.o
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
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/openbmc/linux/drivers/cache/
H A Dax45mp_cache.c1 // SPDX-License-Identifier: GPL-2.0
3 * non-coherent cache functions for Andes AX45MP
10 #include <linux/dma-direction.h>
14 #include <asm/dma-noncoherent.h>
23 /* D-cache operation */
25 #define AX45MP_CCTL_L1D_VA_WB 1 /* Write-back an L1 cache entry */
35 #define AX45MP_CCTL_L2_PA_WB 0x9 /* Write-back an L2 cache entry */
89 /* Write-back L1 and L2 cache entry */
115 start = start & (~(line_size - 1)); in ax45mp_dma_cache_inv()
116 end = ((end + line_size - 1) & (~(line_size - 1))); in ax45mp_dma_cache_inv()
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/openbmc/u-boot/board/freescale/t102xrdb/
H A DREADME2 ------------------
4 combines two or one 64-bit Power Architecture e5500 core respectively with high
9 and general-purpose embedded computing. Its high level of integration offers
14 - two e5500 cores, each with a private 256 KB L2 cache
15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
16 - Three levels of instructions: User, supervisor, and hypervisor
17 - Independent boot and reset
18 - Secure boot capability
19 - 256 KB shared L3 CoreNet platform cache (CPC)
20 - Interconnect CoreNet platform
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/openbmc/linux/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 timebase-frequency = <3000000>;
24 i-cache-block-size = <64>;
25 i-cache-size = <65536>;
26 i-cache-sets = <512>;
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/openbmc/linux/drivers/of/
H A Daddress.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/dma-direct.h> /* for bus_dma_region */
31 while (na--) in of_dump_addr()
79 return da - cp; in of_bus_default_map()
88 addr[na - 2] = cpu_to_be32(a >> 32); in of_bus_default_translate()
89 addr[na - 1] = cpu_to_be32(a & 0xffffffffu); in of_bus_default_translate()
114 cp = of_read_number(range + 1, na - 1); in of_bus_default_flags_map()
116 da = of_read_number(addr + 1, na - 1); in of_bus_default_flags_map()
122 return da - cp; in of_bus_default_flags_map()
128 return of_bus_default_translate(addr + 1, offset, na - 1); in of_bus_default_flags_translate()
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/openbmc/linux/arch/riscv/boot/dts/allwinner/
H A Dsunxi-d1s-t113.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
4 #include <dt-bindings/clock/sun6i-rtc.h>
5 #include <dt-bindings/clock/sun8i-de2.h>
6 #include <dt-bindings/clock/sun8i-tcon-top.h>
7 #include <dt-bindings/clock/sun20i-d1-ccu.h>
8 #include <dt-bindings/clock/sun20i-d1-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/reset/sun8i-de2.h>
11 #include <dt-bindings/reset/sun20i-d1-ccu.h>
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/openbmc/u-boot/board/freescale/t102xqds/
H A DREADME2 ------------------
4 combines two or one 64-bit Power Architecture e5500 core respectively with high
9 and general-purpose embedded computing. Its high level of integration offers
14 - two e5500 cores, each with a private 256 KB L2 cache
15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
16 - Three levels of instructions: User, supervisor, and hypervisor
17 - Independent boot and reset
18 - Secure boot capability
19 - 256 KB shared L3 CoreNet platform cache (CPC)
20 - Interconnect CoreNet platform
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/openbmc/linux/drivers/scsi/
H A D53c700.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* Driver for 53c700 and 53c700-66 chips from NCR and Symbios
17 /* Turn on for general debugging---too verbose for normal use */
41 #define NCR_700_LUN_MASK (NCR_700_MAX_LUNS - 1)
81 * for the annoying SCSI-2 requirement for LUN information in
109 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata; in NCR_700_get_sense_cmnd()
111 return hostdata->cmnd; in NCR_700_get_sense_cmnd()
117 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata; in NCR_700_set_depth()
119 hostdata->depth = depth; in NCR_700_set_depth()
124 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata; in NCR_700_get_depth()
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H A D53c700.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /* NCR (or Symbios) 53c700 and 53c700-66 Driver
6 **-----------------------------------------------------------------------------
9 **-----------------------------------------------------------------------------
20 * The 700-66 can at least do synchronous SCSI up to 10MHz.
27 * minimal wrapper for the purpose---see the NCR_D700 driver for
54 * Bogendoerfer). Added missing SCp->request_bufflen initialisation
73 * Added support for the 53c710 chip (in 53c700 emulation mode only---no
94 * dma cache flushing operations for architectures which need it;
119 #include <asm/dma.h>
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/openbmc/linux/arch/riscv/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
169 # https://github.com/llvm/llvm-project/commit/6ab8927931851bb42b2c93a00801dc499d7d9b1e
176 depends on $(cc-option,-fpatchable-function-entry=8)
186 # VA_BITS - PAGE_SHIFT - 3
199 # set if we are running in S-mode and can use SBI calls
206 bool "MMU-based Paged Memory Management Support"
209 Select if you want MMU-based virtualised addressing space
286 This enables function pointer support for non-standard noncoherent
290 def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero)
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/openbmc/qemu/tests/data/qobject/
H A Dqdict.txt1 00-INDEX: 333
55 3.Early-stage: 9993
56 3w-9xxx.c: 77318
57 3w-9xxx.h: 26357
58 3w-xxxx.c: 85227
59 3w-xxxx.h: 16846
71 4level-fixup.h: 1028
110 6xx-suspend.S: 1086
148 8250-platform.c: 1091
161 83xx-512x-pci.txt: 1323
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/openbmc/linux/drivers/irqchip/
H A Dirq-gic-v3.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
24 #include <linux/irqchip/arm-gic-common.h>
25 #include <linux/irqchip/arm-gic-v3.h>
26 #include <linux/irqchip/irq-partition-percpu.h>
29 #include <linux/arm-smccc.h>
36 #include "irq-gic-common.h"
83 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
87 * When security is enabled, non-secure priority values from the (re)distributor
91 * If SCR_EL3.FIQ == 1, the values written to/read from PMR and RPR at non-secure
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H A Dirq-gic-v3-its.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
34 #include <linux/irqchip/arm-gic-v3.h>
35 #include <linux/irqchip/arm-gic-v4.h>
40 #include "irq-gic-common.h"
65 * Collection structure - just an ID, and a redistributor address to
75 * The ITS_BASER structure - contains memory information, cached
88 * The ITS structure - contains most of the infrastructure, with the
89 * top-level MSI domain, the command queue, the collections, and the
122 #define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS))
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/openbmc/linux/
H A Dopengrok1.0.log1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa
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H A Dopengrok2.0.log1 2024-12-28 20:05:26.116-0600 FINEST t586 Statistics.logIt: Added: '/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/rtnetlink.sh' (ShAnalyzer) (took 79 ms)
2 2024-12-28 20:05:26.112-0600 FINER t592 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/qemu',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/qemu/chardev/spice.c'
3 2024-12-28 20:05:26.116-0600 FINEST t592 Statistics.logIt: Added: '/openbmc/qemu/chardev/spice.c' (CAnalyzer) (took 33 ms)
4 2024-1
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/openbmc/linux/arch/x86/kvm/vmx/
H A Dvmx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
31 #include <linux/entry-kvm.h>
49 #include <asm/spec-ctrl.h>
135 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
187 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
203 /* Default doubles per-vcpu window every exit. */
207 /* Default resets per-vcpu window every exit to ple_window. */
215 /* Default is SYSTEM mode, 1 for host-guest mode (which is BROKEN) */
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