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/openbmc/linux/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/
H A Duncore-ddrc.json5 "BriefDescription": "DDRC total write operations",
6 "PublicDescription": "DDRC total write operations",
7 "Unit": "hisi_sccl,ddrc"
12 "BriefDescription": "DDRC total read operations",
13 "PublicDescription": "DDRC total read operations",
14 "Unit": "hisi_sccl,ddrc"
19 "BriefDescription": "DDRC write commands",
20 "PublicDescription": "DDRC write commands",
21 "Unit": "hisi_sccl,ddrc"
26 "BriefDescription": "DDRC read commands",
[all …]
H A Duncore-hha.json48 "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 64 bytes",
49 "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 64bytes",
55 … "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
56 … "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
62 … "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
63 … "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
69 … "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
70 … "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dimx8m-ddrc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
13 The DDRC block is integrated in i.MX8M for interfacing with DDR based
20 The Linux driver for the DDRC doesn't even map registers (they're included
28 - fsl,imx8mn-ddrc
29 - fsl,imx8mm-ddrc
30 - fsl,imx8mq-ddrc
31 - const: fsl,imx8m-ddrc
36 Base address and size of DDRC CTL area.
37 This is not currently mapped by the imx8m-ddrc driver.
64 ddrc: memory-controller@3d400000 {
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dsnps,dw-umctl2-ddrc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
28 const: snps,ddrc-3.80a
30 const: snps,dw-umctl2-ddrc
32 const: xlnx,zynqmp-ddrc-2.40a
36 DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"
61 reference clock, DDRC core clock, Scrubber standalone clock
62 (synchronous to the DDRC clock).
96 compatible = "xlnx,zynqmp-ddrc-2.40a";
107 compatible = "snps,dw-umctl2-ddrc";
H A Dxlnx,zynq-ddrc-a05.yaml4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#
20 const: xlnx,zynq-ddrc-a05
34 compatible = "xlnx,zynq-ddrc-a05";
/openbmc/u-boot/board/atmel/sama5d2_xplained/
H A Dsama5d2_xplained.c102 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) in ddrc_conf() argument
104 ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); in ddrc_conf()
106 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddrc_conf()
115 ddrc->rtr = 0x511; in ddrc_conf()
117 ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddrc_conf()
126 ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET | in ddrc_conf()
131 ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET | in ddrc_conf()
/openbmc/u-boot/board/atmel/sama5d27_som1_ek/
H A Dsama5d27_som1_ek.c101 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) in ddrc_conf() argument
103 ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddrc_conf()
105 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddrc_conf()
114 ddrc->rtr = 0x511; in ddrc_conf()
116 ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | in ddrc_conf()
125 ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | in ddrc_conf()
130 ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | in ddrc_conf()
/openbmc/linux/Documentation/devicetree/bindings/interconnect/
H A Dfsl,imx8m-noc.yaml53 fsl,ddrc:
81 fsl,ddrc = <&ddrc>;
96 ddrc: memory-controller@3d400000 {
97 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
/openbmc/linux/drivers/perf/hisilicon/
H A Dhisi_uncore_ddrc_pmu.c3 * HiSilicon SoC DDRC uncore Hardware event counters support
21 /* DDRC register definition in v1 */
37 /* DDRC register definition in v2 */
46 /* DDRC has 8-counters */
110 * For DDRC PMU v1, event has been mapped to fixed-purpose counter by hardware,
172 /* For DDRC PMU, we use event code as counter index */ in hisi_ddrc_pmu_v1_get_event_idx()
301 * Use the SCCL_ID and DDRC channel ID to identify the in hisi_ddrc_pmu_init_data()
302 * DDRC PMU, while SCCL_ID is in MPIDR[aff2]. in hisi_ddrc_pmu_init_data()
306 dev_err(&pdev->dev, "Can not read ddrc channel-id!\n"); in hisi_ddrc_pmu_init_data()
312 dev_err(&pdev->dev, "Can not read ddrc sccl-id!\n"); in hisi_ddrc_pmu_init_data()
[all …]
H A Dhisi_uncore_pmu.h103 /* For DDRC PMU v2: each DDRC has more than one DMC */
/openbmc/u-boot/arch/mips/mach-jz47xx/include/mach/
H A Djz4780_dram.h85 /* DDRC Status Register */
94 /* DDRC Configure Register */
140 /* DDRC Control Register */
172 /* DDRC Load-Mode-Register */
199 /* DDRC Timing Config Register 1 */
219 /* DDRC Timing Config Register 2 */
229 /* DDRC Timing Config Register 3 */
244 /* DDRC Timing Config Register 4 */
260 /* DDRC Timing Config Register 5 */
270 /* DDRC Timing Config Register 6 */
[all …]
/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dddr.c21 * @ddrc_regs_val: DDRC registers value
27 void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val, in mx7_dram_cfg()
32 struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR; in mx7_dram_cfg()
107 * Description: extract the current DRAM size from the DDRC registers
113 struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR; in imx_ddr_size()
/openbmc/linux/tools/perf/pmu-events/arch/test/test_soc/cpu/
H A Duncore.json5 "BriefDescription": "DDRC write commands",
6 "PublicDescription": "DDRC write commands",
7 "Unit": "hisi_sccl,ddrc"
/openbmc/linux/arch/arm/mach-zynq/
H A Dpm.c58 ddrc_base = zynq_pm_ioremap("xlnx,zynq-ddrc-a05"); in zynq_pm_late_init()
60 pr_warn("%s: Unable to map DDRC IO memory.\n", __func__); in zynq_pm_late_init()
63 * Enable DDRC clock stop feature. The HW takes care of in zynq_pm_late_init()
/openbmc/linux/Documentation/admin-guide/perf/
H A Dhisi-pmu.rst6 such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
20 HHA and DDRC etc. The available events and configuration options shall
23 /sys/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>/, or
24 /sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
27 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
H A Dalibaba_pmu.rst28 based on DDRC core clock.
53 By counting the READ, WRITE and RMW commands sent to the DDRC through the HIF
/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dsoc.c115 /* disables propagation of barrier transactions to DDRC from CCI400 */ in erratum_a008850_early()
118 /* disable the re-ordering in DDRC */ in erratum_a008850_early()
132 /* enable propagation of barrier transactions to DDRC from CCI400 */ in erratum_a008850_post()
135 /* enable the re-ordering in DDRC */ in erratum_a008850_post()
/openbmc/linux/drivers/power/reset/
H A Dat91-sama5d2_shdwc.c89 struct ddrc_reg_config ddrc; member
271 .ddrc = {
288 .ddrc = {
386 if (at91_shdwc->rcfg->ddrc.type_mask) { in at91_shdwc_probe()
403 at91_shdwc->rcfg->ddrc.type_offset) & in at91_shdwc_probe()
404 at91_shdwc->rcfg->ddrc.type_mask; in at91_shdwc_probe()
/openbmc/u-boot/board/hisilicon/hikey/
H A DREADME125 INFO: succeed to set ddrc 150mhz
127 INFO: succeed to set ddrc 266mhz
129 INFO: succeed to set ddrc 400mhz
131 INFO: succeed to set ddrc 533mhz
133 INFO: succeed to set ddrc 800mhz
/openbmc/u-boot/arch/arm/include/asm/arch-mx7/
H A Dmx7-ddr.h13 /* DDRC Registers (DDRC_IPS_BASE_ADDR) */
14 struct ddrc { struct
150 void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
/openbmc/linux/drivers/devfreq/
H A Dimx8m-ddrc.c262 dev_err(dev, "ddrc failed freq switch to %lu from %lu: error %d. now at %lu\n", in imx8m_ddrc_target()
265 dev_err(dev, "ddrc failed freq update to %lu from %lu, now at %lu\n", in imx8m_ddrc_target()
268 dev_dbg(dev, "ddrc freq set to %lu (was %lu)\n", in imx8m_ddrc_target()
441 { .compatible = "fsl,imx8m-ddrc", },
449 .name = "imx8m-ddrc-devfreq",
H A DMakefile13 obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
/openbmc/linux/tools/perf/pmu-events/
H A Dempty-pmu-events.c43 .desc = "DDRC write commands. Unit: hisi_sccl,ddrc ",
45 .long_desc = "DDRC write commands",
46 .pmu = "hisi_sccl,ddrc",
/openbmc/u-boot/arch/arm/mach-zynq/
H A DMakefile11 obj-y += ddrc.o
H A DKconfig31 bool "Zynq DDRC initialization"

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