184508131SSerge Semin# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 284508131SSerge Semin%YAML 1.2 384508131SSerge Semin--- 484508131SSerge Semin$id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml# 584508131SSerge Semin$schema: http://devicetree.org/meta-schemas/core.yaml# 684508131SSerge Semin 784508131SSerge Semintitle: Zynq A05 DDR Memory Controller 884508131SSerge Semin 984508131SSerge Seminmaintainers: 1084508131SSerge Semin - Krzysztof Kozlowski <krzk@kernel.org> 11d5c421d2SMichal Simek - Michal Simek <michal.simek@amd.com> 1284508131SSerge Semin 1384508131SSerge Semindescription: 1484508131SSerge Semin The Zynq DDR ECC controller has an optional ECC support in half-bus width 15*47aab533SBjorn Helgaas (16-bit) configuration. It is capable of correcting single bit ECC errors 1684508131SSerge Semin and detecting double bit ECC errors. 1784508131SSerge Semin 1884508131SSerge Seminproperties: 1984508131SSerge Semin compatible: 2084508131SSerge Semin const: xlnx,zynq-ddrc-a05 2184508131SSerge Semin 2284508131SSerge Semin reg: 2384508131SSerge Semin maxItems: 1 2484508131SSerge Semin 2584508131SSerge Seminrequired: 2684508131SSerge Semin - compatible 2784508131SSerge Semin - reg 2884508131SSerge Semin 2984508131SSerge SeminadditionalProperties: false 3084508131SSerge Semin 3184508131SSerge Seminexamples: 3284508131SSerge Semin - | 3384508131SSerge Semin memory-controller@f8006000 { 3484508131SSerge Semin compatible = "xlnx,zynq-ddrc-a05"; 3584508131SSerge Semin reg = <0xf8006000 0x1000>; 3684508131SSerge Semin }; 3784508131SSerge Semin... 38