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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Drohm,bd9576-pmic.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd9576-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
14 powering the R-Car series processors.
21 - rohm,bd9576
22 - rohm,bd9573
32 rohm,vout1-en-low:
35 controlled by a GPIO. This is dictated by state of vout1-en pin during
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/openbmc/u-boot/board/hisilicon/hikey/
H A DREADME4 HiKey is the first certified 96Boards Consumer Edition board. The board/SoC has: -
5 * HiSilicon Kirin 6220 eight-core ARM Cortex-A53 64-bit SoC running at 1.2GHz.
6 * ARM Mali 450-MP4 GPU
12 The HiKey schematic can be found here: -
13 https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey620/hardware-docs/HiKey_s…
15 The SoC datasheet can be found here: -
16 …boards/documentation/blob/master/consumer/hikey/hikey620/hardware-docs/Hi6220V100_Multi-Mode_Appli…
18 Currently the u-boot port supports: -
24 The HiKey U-Boot port has been tested with l-loader, booting ATF, which then boots
25 U-Boot as the bl33.bin executable.
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/openbmc/pldm/oem/ampere/event/
H A Doem_event_manager.hpp8 #include "platform-mc/manager.hpp"
85 * Bit 30:24 | Media slot number (0 - 63) This field can be used by UEFI
90 * Bit 22 | Action: 0 - Insertion 1 - Removal
130 namespace ddr namespace
145 } // namespace ddr
208 * Bit 15:8 | VR status byte high - The bit definition is the same as the
210 * Bit 7:0 | VR status byte low - The bit definition is the same as the
249 * @param[in] request - the request message of sensor event
250 * @param[in] payloadLength - the payload length of sensor event
251 * @param[in] formatVersion - the format version of sensor event
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H A Doem_event_manager.cpp12 #include <systemd/sd-journal.h>
14 #include <phosphor-logging/lg2.hpp>
29 namespace ddr_status = ddr::status;
52 An array of possible boot status of DDR training stage.
56 " progress started", " in-progress", " progress completed"};
104 {boot_stage::DDR_INITIALIZATION, "DDR initialization"},
105 {boot_stage::DDR_TRAINING, "DDR training"},
106 {boot_stage::S0_DDR_TRAINING_FAILURE, "DDR training failure"},
109 {boot_stage::S1_DDR_TRAINING_FAILURE, "DDR training failure"},
114 A map between DDR status and logging strings.
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/openbmc/linux/drivers/regulator/
H A Dbd9576-regulator.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/mfd/rohm-bd957x.h>
11 #include <linux/mfd/rohm-generic.h>
137 const struct regulator_desc *desc = rdev->desc; in bd957x_vout34_list_voltage()
138 int multiplier = selector & desc->vsel_mask & 0x7f; in bd957x_vout34_list_voltage()
145 return desc->fixed_uV - tune; in bd957x_vout34_list_voltage()
147 return desc->fixed_uV + tune; in bd957x_vout34_list_voltage()
153 const struct regulator_desc *desc = rdev->desc; in bd957x_list_voltage()
154 int index = selector & desc->vsel_mask & 0x7f; in bd957x_list_voltage()
157 index += desc->n_voltages/2; in bd957x_list_voltage()
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/openbmc/linux/drivers/mtd/nand/raw/
H A Ddenali.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright © 2009-2010, Intel Corporation and its suppliers.
6 * Copyright (c) 2017-2019 Socionext Inc.
12 #include <linux/dma-mapping.h>
23 #define DENALI_NAND_NAME "denali-nand"
31 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
39 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
41 #define DENALI_INVALID_BANK -1
50 return container_of(chip->controller, struct denali_controller, in to_denali_controller()
55 * Direct Addressing - the slave address forms the control information (command
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/openbmc/u-boot/drivers/clk/
H A Dclk_stm32mp1.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
7 #include <clk-uclass.h>
15 #include <dt-bindings/clock/stm32mp1-clks.h>
16 #include <dt-bindings/clock/stm32mp1-clksrc.h>
380 u8 sel; member
406 const struct stm32mp1_clk_sel *sel; member
424 .sel = (s), \
434 .sel = _UNKNOWN_SEL, \
444 .sel = (s), \
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/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
19 stdout-path = "serial2:115200n8";
28 * - Rails that only connect to the EC (or devices that the EC talks to)
30 * - Rails _are_ included if the rails go to the AP even if the AP
39 * - The EC controls the enable and the EC always enables a rail as
41 * - The rails are actually connected to each other by a jumper and
46 ppvar_sys: ppvar-sys {
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/openbmc/u-boot/arch/arm/dts/
H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
14 u-boot,dm-pre-reloc;
15 stdout-path = "serial2:115200n8";
16 u-boot,spl-boot-order = &spi_flash;
20 u-boot,spl-payload-offset = <0x40000>;
29 * - Rails that only connect to the EC (or devices that the EC talks to)
31 * - Rails _are_ included if the rails go to the AP even if the AP
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/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp15xc-lxa-tac.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
9 #include "stm32mp15xx-osd32.dtsi"
10 #include "stm32mp15xxac-pinctrl.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/pwm/pwm.h>
28 stdout-path = &uart4;
31 led-controller-0 {
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/openbmc/u-boot/arch/arm/mach-exynos/
H A Dexynos5_setup.h1 /* SPDX-License-Identifier: GPL-2.0+ */
168 /* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
174 /* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
239 /* AUDIO CLK SEL */
889 /* Errors that we can encourter in low-level setup */
892 SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
893 SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
900 * @param reset Reset DDR PHY during initialization.
912 * @param phy0_con16 Register address for dmc_phy0->phy_con16
913 * @param phy1_con16 Register address for dmc_phy1->phy_con16
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/openbmc/u-boot/drivers/usb/gadget/
H A Ddwc2_udc_otg.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
10 * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
15 * Ported to u-boot:
32 #include <asm/mach-types.h>
68 static const char driver_name[] = "dwc2-udc";
69 static const char ep0name[] = "ep0-control";
115 the_controller->gadget.dev.device_data = p; in set_udc_gadget_private_data()
120 return gadget->dev.device_data; in get_udc_gadget_private_data()
148 return !!(readl(&reg->gintsts) & INT_RESET); in dfu_usb_get_reset()
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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam437x-gp-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/pinctrl/am43xx.h>
12 #include <dt-bindings/pwm/pwm.h>
13 #include <dt-bindings/gpio/gpio.h>
17 compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
24 stdout-path = &uart0;
27 evm_v3_3d: fixedregulator-v3_3d {
28 compatible = "regulator-fixed";
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/openbmc/linux/drivers/gpu/drm/radeon/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
698 // [3] Transmitter Sel
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/openbmc/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
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/openbmc/linux/drivers/memory/tegra/
H A Dtegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
15 #include <linux/interconnect-provider.h>
512 /* protect shared rate-change code path */
521 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
522 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
530 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
533 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
539 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
547 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_seq_disable_auto_cal()
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/openbmc/fb-ipmi-oem/src/
H A Doemcommands.cpp3 * Copyright (c) 2018-present Facebook.
9 * http://www.apache.org/licenses/LICENSE-2.0
22 #include <ipmid/api-types.hpp>
27 #include <phosphor-logging/log.hpp>
75 constexpr const char* certPath = "/mnt/data/host/bios-rootcert";
81 static constexpr const char* FRU_EEPROM = "/sys/bus/i2c/devices/6-0054/eeprom";
137 ipmi::getDbusProperty(bus, object.second.begin()->first, in getIPObject()
144 variant = ipmi::getDbusProperty(bus, object.second.begin()->first, in getIPObject()
147 objectInfo = std::make_pair(object.first, object.second.begin()->first); in getIPObject()
149 // if LinkLocalIP found look for Non-LinkLocalIP in getIPObject()
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/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-apalis-v1.1.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
16 avdd-pexa-supply = <&vdd2_reg>;
17 avdd-pexb-supply = <&vdd2_reg>;
18 avdd-pex-pll-supply = <&vdd2_reg>;
19 avdd-plle-supply = <&ldo6_reg>;
20 hvdd-pex-supply = <&reg_module_3v3>;
21 vddio-pex-ctl-supply = <&reg_module_3v3>;
22 vdd-pexa-supply = <&vdd2_reg>;
23 vdd-pexb-supply = <&vdd2_reg>;
27 nvidia,num-lanes = <4>;
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H A Dtegra30-apalis.dtsi1 // SPDX-License-Identifier: GPL-2.0
15 avdd-pexa-supply = <&vdd2_reg>;
16 avdd-pexb-supply = <&vdd2_reg>;
17 avdd-pex-pll-supply = <&vdd2_reg>;
18 avdd-plle-supply = <&ldo6_reg>;
19 hvdd-pex-supply = <&reg_module_3v3>;
20 vddio-pex-ctl-supply = <&reg_module_3v3>;
21 vdd-pexa-supply = <&vdd2_reg>;
22 vdd-pexb-supply = <&vdd2_reg>;
26 nvidia,num-lanes = <4>;
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H A Dtegra114-dalmore.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include <dt-bindings/input/input.h>
23 stdout-path = "serial0:115200n8";
34 hdmi-supply = <&vdd_5v0_hdmi>;
35 vdd-supply = <&vdd_hdmi_reg>;
36 pll-supply = <&palmas_smps3_reg>;
38 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
39 nvidia,hpd-gpio =
46 avdd-dsi-csi-supply = <&avdd_1v2_reg>;
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/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsc8280xp.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
9 #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
12 #include <dt-bindings/interconnect/qcom,osm-l3.h>
13 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h>
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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_psr.c44 * Since Haswell Display controller supports Panel Self-Refresh on display
48 * request to DDR memory completely as long as the frame buffer for that
58 * The implementation uses the hardware-based PSR support which automatically
59 * enters/exits self-refresh mode. The hardware takes care of sending the
62 * changes to know when to exit self-refresh mode again. Unfortunately that
67 * issues the self-refresh re-enable code is done from a work queue, which
75 * entry/exit allows the HW to enter a low-power state even when page flipping
91 * EDP_PSR_DEBUG[16]/EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw-skl):
155 * In standby mode (as opposed to link-off) this makes no difference
169 * The rest of the bits are more self-explanatory and/or
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/openbmc/linux/drivers/mmc/host/
H A Dmtk-sd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, 2022 MediaTek Inc.
11 #include <linux/dma-mapping.h>
34 #include <linux/mmc/slot-gpio.h>
41 /*---
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/openbmc/linux/
H A Dopengrok0.0.log1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz'
2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz'
3 2024-12-2
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/openbmc/
Dopengrok1.0.log1 2025-01-09 03:00:44.932-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-01-09 03:00:45.045-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
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