Lines Matching +full:ddr +full:- +full:sel +full:- +full:low

1 /* SPDX-License-Identifier: GPL-2.0+ */
168 /* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
174 /* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
239 /* AUDIO CLK SEL */
889 /* Errors that we can encourter in low-level setup */
892 	SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
893 	SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
900  * @param reset         Reset DDR PHY during initialization.
912  * @param phy0_con16	Register address for dmc_phy0->phy_con16
913  * @param phy1_con16	Register address for dmc_phy1->phy_con16
914  * @param phy0_con17	Register address for dmc_phy0->phy_con17
915  * @param phy1_con17	Register address for dmc_phy1->phy_con17
916  * @return 0 if ok, -1 on error
925  * @param directcmd	Register address for dmc_phy->directcmd
933  * @param directcmd	Register address for dmc_phy->directcmd
942  * @param phycontrol0	Register address for dmc_phy->phycontrol0
943  * @param ddr_mode	Type of DDR memory