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/openbmc/linux/arch/m68k/ifpsp060/
H A Dpfpsp.sa1 dc.l $60ff0000,$17400000,$60ff0000,$15f40000
2 dc.l $60ff0000,$02b60000,$60ff0000,$04700000
3 dc.l $60ff0000,$1b100000,$60ff0000,$19aa0000
4 dc.l $60ff0000,$1b5a0000,$60ff0000,$062e0000
5 dc.l $60ff0000,$102c0000,$51fc51fc,$51fc51fc
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $2f00203a,$ff2c487b,$0930ffff,$fef8202f
10 dc.l $00044e74,$00042f00,$203afef2,$487b0930
[all …]
H A Dfplsp.sa1 dc.l $60ff0000,$238e0000,$60ff0000,$24200000
2 dc.l $60ff0000,$24b60000,$60ff0000,$11060000
3 dc.l $60ff0000,$11980000,$60ff0000,$122e0000
4 dc.l $60ff0000,$0f160000,$60ff0000,$0fa80000
5 dc.l $60ff0000,$103e0000,$60ff0000,$12ae0000
6 dc.l $60ff0000,$13400000,$60ff0000,$13d60000
7 dc.l $60ff0000,$05ae0000,$60ff0000,$06400000
8 dc.l $60ff0000,$06d60000,$60ff0000,$213e0000
9 dc.l $60ff0000,$21d00000,$60ff0000,$22660000
10 dc.l $60ff0000,$16160000,$60ff0000,$16a80000
[all …]
H A Ditest.sa1 dc.l $60ff0000,$005c5465,$7374696e,$67203638
2 dc.l $30363020,$49535020,$73746172,$7465643a
3 dc.l $0a007061,$73736564,$0a002066,$61696c65
4 dc.l $640a0000,$4a80660e,$487affe8,$61ff0000
5 dc.l $4f9a588f,$4e752f01,$61ff0000,$4fa4588f
6 dc.l $487affd8,$61ff0000,$4f82588f,$4e754e56
7 dc.l $ff6048e7,$3f3c487a,$ff9e61ff,$00004f6c
8 dc.l $588f42ae,$ff78487b,$01700000,$00ea61ff
9 dc.l $00004f58,$588f61ff,$000000f0,$61ffffff
10 dc.l $ffa642ae,$ff78487b,$01700000,$0af661ff
[all …]
H A Dftest.sa1 dc.l $60ff0000,$00d40000,$60ff0000,$016c0000
2 dc.l $60ff0000,$01a80000,$54657374,$696e6720
3 dc.l $36383036,$30204650,$53502073,$74617274
4 dc.l $65643a0a,$00546573,$74696e67,$20363830
5 dc.l $36302046,$50535020,$756e696d,$706c656d
6 dc.l $656e7465,$6420696e,$73747275,$6374696f
7 dc.l $6e207374,$61727465,$643a0a00,$54657374
8 dc.l $696e6720,$36383036,$30204650,$53502065
9 dc.l $78636570,$74696f6e,$20656e61,$626c6564
10 dc.l $20737461,$72746564,$3a0a0070,$61737365
[all …]
H A Dilsp.sa1 dc.l $60ff0000,$01fe0000,$60ff0000,$02080000
2 dc.l $60ff0000,$04900000,$60ff0000,$04080000
3 dc.l $60ff0000,$051e0000,$60ff0000,$053c0000
4 dc.l $60ff0000,$055a0000,$60ff0000,$05740000
5 dc.l $60ff0000,$05940000,$60ff0000,$05b40000
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
10 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
[all …]
/openbmc/qemu/target/openrisc/
H A Dtranslate.c61 static inline bool is_user(DisasContext *dc) in is_user() argument
66 return !(dc->tb_flags & TB_FLAGS_SM); in is_user()
134 static void gen_exception(DisasContext *dc, unsigned int excp) in gen_exception() argument
139 static void gen_illegal_exception(DisasContext *dc) in gen_illegal_exception() argument
141 tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); in gen_illegal_exception()
142 gen_exception(dc, EXCP_ILLEGAL); in gen_illegal_exception()
143 dc->base.is_jmp = DISAS_NORETURN; in gen_illegal_exception()
146 static bool check_v1_3(DisasContext *dc) in check_v1_3() argument
148 return dc->avr >= 0x01030000; in check_v1_3()
151 static bool check_of32s(DisasContext *dc) in check_of32s() argument
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer.h32 struct dc;
34 void dcn10_hw_sequencer_construct(struct dc *dc);
38 struct dc *dc,
42 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
46 struct dc *dc);
48 struct dc *dc,
51 struct dc *dc,
54 struct dc *dc,
57 void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);
59 struct dc *dc,
[all …]
/openbmc/linux/drivers/dma/
H A Dtxx9dmac.c24 static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc) in __dma_regs() argument
26 return dc->ch_regs; in __dma_regs()
30 const struct txx9dmac_chan *dc) in __dma_regs32() argument
32 return dc->ch_regs; in __dma_regs32()
35 #define channel64_readq(dc, name) \ argument
36 __raw_readq(&(__dma_regs(dc)->name))
37 #define channel64_writeq(dc, name, val) \ argument
38 __raw_writeq((val), &(__dma_regs(dc)->name))
39 #define channel64_readl(dc, name) \ argument
40 __raw_readl(&(__dma_regs(dc)->name))
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dhw_sequencer.h50 struct dc *dc; member
56 struct dc *dc; member
67 const struct dc *dc; member
73 struct dc *dc; member
78 struct dc *dc; member
106 struct dc *dc; member
112 struct dc *dc; member
181 void (*hardware_release)(struct dc *dc);
188 void (*init_hw)(struct dc *dc);
189 void (*power_down_on_boot)(struct dc *dc);
[all …]
H A Dhw_sequencer_private.h75 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
76 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
77 void (*init_pipes)(struct dc *dc, struct dc_state *context);
78 void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
79 void (*update_plane_addr)(const struct dc *dc,
81 void (*plane_atomic_disconnect)(struct dc *dc,
83 void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
84 bool (*set_input_transfer_func)(struct dc *dc,
87 bool (*set_output_transfer_func)(struct dc *dc,
90 void (*power_down)(struct dc *dc);
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hwseq.h36 struct dc *dc,
39 struct dc *dc,
41 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
42 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
43 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
45 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
47 void dcn20_program_output_csc(struct dc *dc,
55 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
57 struct dc *dc,
61 struct dc *dc,
[all …]
/openbmc/linux/drivers/tty/
H A Dnozomi.c331 struct nozomi *dc; member
479 static void nozomi_setup_memory(struct nozomi *dc) in nozomi_setup_memory() argument
481 void __iomem *offset = dc->base_addr + dc->config_table.dl_start; in nozomi_setup_memory()
488 dc->port[PORT_MDM].dl_addr[CH_A] = offset; in nozomi_setup_memory()
489 dc->port[PORT_MDM].dl_addr[CH_B] = in nozomi_setup_memory()
490 (offset += dc->config_table.dl_mdm_len1); in nozomi_setup_memory()
491 dc->port[PORT_MDM].dl_size[CH_A] = in nozomi_setup_memory()
492 dc->config_table.dl_mdm_len1 - buff_offset; in nozomi_setup_memory()
493 dc->port[PORT_MDM].dl_size[CH_B] = in nozomi_setup_memory()
494 dc->config_table.dl_mdm_len2 - buff_offset; in nozomi_setup_memory()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c27 #include "dc.h"
81 dc->ctx
84 dc->ctx->logger
91 * DC is the OS-agnostic component of the amdgpu DC driver.
93 * DC maintains and validates a set of structs representing the state of the
96 * Main DC HW structs:
98 * struct dc - The central struct. One per driver. Created on driver load,
102 * Used as a backpointer by most other structs in dc.
115 * Main dc state structs:
118 * these structs in dc->current_state representing the currently programmed state.
[all …]
H A Ddc_link_exports.c27 * This file provides single entrance to link functionality declared in dc
32 * When exporting a new link related dc function, add function declaration in
33 * dc.h with detail interface documentation, then add function implementation
38 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index) in dc_get_link_at_index() argument
40 return dc->links[link_index]; in dc_get_link_at_index()
43 void dc_get_edp_links(const struct dc *dc, in dc_get_edp_links() argument
50 for (i = 0; i < dc->link_count; i++) { in dc_get_edp_links()
52 if (!dc->links[i]) in dc_get_edp_links()
54 if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP) { in dc_get_edp_links()
55 edp_links[*edp_num] = dc->links[i]; in dc_get_edp_links()
[all …]
H A Ddc_stream.c28 #include "dc.h"
35 #define DC_LOGGER dc->ctx->logger
48 if (stream->ctx->dc->caps.dual_link_dvi && in update_stream_signal()
203 if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign) in dc_copy_stream()
212 * dc_stream_get_status_from_state - Get stream status from given dc state
213 * @state: DC state to find the stream status in
216 * The given stream is expected to exist in the given dc state. Otherwise, NULL
240 * The given stream is expected to exist in dc->current_state. Otherwise, NULL
246 struct dc *dc = stream->ctx->dc; in dc_stream_get_status() local
247 return dc_stream_get_status_from_state(dc->current_state, stream); in dc_stream_get_status()
[all …]
/openbmc/qemu/target/microblaze/
H A Dtranslate.c81 static int typeb_imm(DisasContext *dc, int x) in typeb_imm() argument
83 if (dc->tb_flags & IMM_FLAG) { in typeb_imm()
84 return deposit32(dc->ext_imm, 0, 16, x); in typeb_imm()
92 static void t_sync_flags(DisasContext *dc) in t_sync_flags() argument
95 if ((dc->tb_flags ^ dc->base.tb->flags) & IFLAGS_TB_MASK) { in t_sync_flags()
96 tcg_gen_movi_i32(cpu_iflags, dc->tb_flags & IFLAGS_TB_MASK); in t_sync_flags()
100 static void gen_raise_exception(DisasContext *dc, uint32_t index) in gen_raise_exception() argument
103 dc->base.is_jmp = DISAS_NORETURN; in gen_raise_exception()
106 static void gen_raise_exception_sync(DisasContext *dc, uint32_t index) in gen_raise_exception_sync() argument
108 t_sync_flags(dc); in gen_raise_exception_sync()
[all …]
/openbmc/linux/drivers/md/
H A Ddm-delay.c54 struct delay_c *dc = from_timer(dc, t, delay_timer); in handle_delayed_timer() local
56 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer()
59 static void queue_timeout(struct delay_c *dc, unsigned long expires) in queue_timeout() argument
61 mutex_lock(&dc->timer_lock); in queue_timeout()
63 if (!timer_pending(&dc->delay_timer) || expires < dc->delay_timer.expires) in queue_timeout()
64 mod_timer(&dc->delay_timer, expires); in queue_timeout()
66 mutex_unlock(&dc->timer_lock); in queue_timeout()
81 static struct bio *flush_delayed_bios(struct delay_c *dc, int flush_all) in flush_delayed_bios() argument
89 list_for_each_entry_safe(delayed, next, &dc->delayed_bios, list) { in flush_delayed_bios()
108 queue_timeout(dc, next_expires); in flush_delayed_bios()
[all …]
/openbmc/qemu/target/sparc/
H A Dtranslate.c217 static void gen_update_fprs_dirty(DisasContext *dc, int rd) in gen_update_fprs_dirty() argument
223 if (!(dc->fprs_dirty & bit)) { in gen_update_fprs_dirty()
224 dc->fprs_dirty |= bit; in gen_update_fprs_dirty()
246 static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src) in gen_load_fpr_F() argument
253 static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v) in gen_store_fpr_F() argument
256 gen_update_fprs_dirty(dc, dst); in gen_store_fpr_F()
266 static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src) in gen_load_fpr_D() argument
273 static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v) in gen_store_fpr_D() argument
276 gen_update_fprs_dirty(dc, dst); in gen_store_fpr_D()
279 static TCGv_i128 gen_load_fpr_Q(DisasContext *dc, unsigned int src) in gen_load_fpr_Q() argument
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_hwseq.c61 dc->ctx->logger
68 static void enable_memory_low_power(struct dc *dc) in enable_memory_low_power() argument
70 struct dce_hwseq *hws = dc->hwseq; in enable_memory_low_power()
73 if (dc->debug.enable_mem_low_power.bits.dmcu) { in enable_memory_low_power()
75 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { in enable_memory_low_power()
81 if (dc->debug.enable_mem_low_power.bits.optc) { in enable_memory_low_power()
86 if (dc->debug.enable_mem_low_power.bits.vga) { in enable_memory_low_power()
91 if (dc->debug.enable_mem_low_power.bits.mpc && in enable_memory_low_power()
92 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode) in enable_memory_low_power()
93 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); in enable_memory_low_power()
[all …]
/openbmc/linux/drivers/md/bcache/
H A Dwriteback.c30 static uint64_t __calc_target_rate(struct cached_dev *dc) in __calc_target_rate() argument
32 struct cache_set *c = dc->disk.c; in __calc_target_rate()
48 div64_u64(bdev_nr_sectors(dc->bdev) << WRITEBACK_SHARE_SHIFT, in __calc_target_rate()
52 div_u64(cache_sectors * dc->writeback_percent, 100); in __calc_target_rate()
61 static void __update_writeback_rate(struct cached_dev *dc) in __update_writeback_rate() argument
83 int64_t target = __calc_target_rate(dc); in __update_writeback_rate()
84 int64_t dirty = bcache_dev_sectors_dirty(&dc->disk); in __update_writeback_rate()
87 div_s64(error, dc->writeback_rate_p_term_inverse); in __update_writeback_rate()
101 struct cache_set *c = dc->disk.c; in __update_writeback_rate()
105 if (dc->writeback_consider_fragment && in __update_writeback_rate()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_hwseq.h31 struct dc;
44 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable);
46 void dcn32_cab_for_ss_control(struct dc *dc, bool enable);
48 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);
53 bool dcn32_set_input_transfer_func(struct dc *dc,
60 bool dcn32_set_output_transfer_func(struct dc *dc,
64 void dcn32_init_hw(struct dc *dc);
66 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);
68 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);
70 void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context);
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/
H A DMakefile71 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
72 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
73 CFLAGS_$(AMDDALPATH)/dc/dml/dcn10/dcn10_fpu.o := $(dml_ccflags)
74 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/dcn20_fpu.o := $(dml_ccflags)
75 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags) $(frame_warn_flag)
76 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags)
77 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags) $(frame_warn_flag)
78 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags)
79 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags) $(frame_warn_flag)
80 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c28 #include "dc.h"
40 dc->ctx->logger
318 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) { in pipe_ctx_to_e2e_pipe_params()
333 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
453 const struct dc *dc, in dcn_bw_calc_rq_dlg_ttu() argument
458 struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml); in dcn_bw_calc_rq_dlg_ttu()
497 input->clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn_bw_calc_rq_dlg_ttu()
500 // dc->dml.logger = pool->base.logger; in dcn_bw_calc_rq_dlg_ttu()
638 static bool dcn_bw_apply_registry_override(struct dc *dc) in dcn_bw_apply_registry_override() argument
642 if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns in dcn_bw_apply_registry_override()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_hwseq.c65 dc->ctx->logger
98 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_mpc_shaper_3dlut()
146 bool dcn30_set_input_transfer_func(struct dc *dc, in dcn30_set_input_transfer_func() argument
150 struct dce_hwseq *hws = dc->hwseq; in dcn30_set_input_transfer_func()
189 bool dcn30_set_output_transfer_func(struct dc *dc, in dcn30_set_output_transfer_func() argument
194 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_output_transfer_func()
226 struct dc *dc, in dcn30_set_writeback() argument
236 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); in dcn30_set_writeback()
237 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; in dcn30_set_writeback()
241 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc, in dcn30_set_writeback()
[all …]
H A Ddcn30_hwseq.h31 struct dc;
33 void dcn30_init_hw(struct dc *dc);
35 struct dc *dc,
39 struct dc *dc,
43 struct dc *dc,
47 struct dc *dc,
51 struct dc *dc,
58 bool dcn30_set_input_transfer_func(struct dc *dc,
61 bool dcn30_set_output_transfer_func(struct dc *dc,
68 bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane,
[all …]

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