Home
last modified time | relevance | path

Searched +full:dc +full:- +full:valid (Results 1 – 25 of 432) sorted by relevance

12345678910>>...18

/openbmc/qemu/hw/watchdog/
H A Dsbsa_gwdt.c14 * option) any later version. See the COPYING file in the top-level directory.
21 #include "hw/qdev-properties.h"
29 .name = "sbsa-gwdt",
59 ret = s->id; in sbsa_gwdt_rread()
75 ret = s->wcs; in sbsa_gwdt_read()
78 ret = s->worl; in sbsa_gwdt_read()
81 ret = s->woru; in sbsa_gwdt_read()
84 ret = s->wcvl; in sbsa_gwdt_read()
87 ret = s->wcvu; in sbsa_gwdt_read()
90 ret = s->id; in sbsa_gwdt_read()
[all …]
H A Dwdt_aspeed.c4 * Copyright (C) 2016-2017 IBM Corp.
7 * COPYING file in the top-level directory.
17 #include "hw/qdev-properties.h"
64 mode = extract32(s->regs[WDT_CTRL], 5, 2); in aspeed_wdt_is_soc_reset_mode()
70 return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE; in aspeed_wdt_is_enabled()
83 return s->regs[WDT_STATUS]; in aspeed_wdt_read()
85 return s->regs[WDT_RELOAD_VALUE]; in aspeed_wdt_read()
88 "%s: read from write-only reg at offset 0x%" in aspeed_wdt_read()
92 return s->regs[WDT_CTRL]; in aspeed_wdt_read()
94 return s->regs[WDT_RESET_WIDTH]; in aspeed_wdt_read()
[all …]
/openbmc/qemu/hw/misc/
H A Dbcm2835_thermal.c4 * Copyright (C) 2019 Philippe Mathieu-Daudé <f4bug@amsat.org>
6 * SPDX-License-Identifier: GPL-2.0-or-later
29 FIELD(STAT, VALID, 10, 1)
33 #define THERMAL_COEFF (-0.538f)
37 return (temp_C - THERMAL_OFFSET_C) / THERMAL_COEFF; in bcm2835_thermal_temp2adc()
47 val = s->ctl; in bcm2835_thermal_read()
51 val = FIELD_DP32(bcm2835_thermal_temp2adc(25), STAT, VALID, true); in bcm2835_thermal_read()
67 s->ctl = value; in bcm2835_thermal_write()
85 .valid.min_access_size = 4,
86 .valid.max_access_size = 4,
[all …]
H A Ddebugexit.c12 #include "hw/qdev-properties.h"
17 #define TYPE_ISA_DEBUG_EXIT_DEVICE "isa-debug-exit"
43 .valid.min_access_size = 1,
44 .valid.max_access_size = 4,
53 memory_region_init_io(&isa->io, OBJECT(dev), &debug_exit_ops, isa, in debug_exit_realizefn()
54 TYPE_ISA_DEBUG_EXIT_DEVICE, isa->iosize); in debug_exit_realizefn()
56 isa->iobase, &isa->io); in debug_exit_realizefn()
66 DeviceClass *dc = DEVICE_CLASS(klass); in debug_exit_class_initfn() local
68 dc->realize = debug_exit_realizefn; in debug_exit_class_initfn()
69 device_class_set_props(dc, debug_exit_properties); in debug_exit_class_initfn()
[all …]
H A Daspeed_sli.c6 * SPDX-License-Identifier: GPL-2.0-or-later
11 #include "qemu/error-report.h"
12 #include "hw/qdev-properties.h"
26 if (reg >= ARRAY_SIZE(s->regs)) { in aspeed_sli_read()
28 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", in aspeed_sli_read()
33 trace_aspeed_sli_read(addr, size, s->regs[reg]); in aspeed_sli_read()
34 return s->regs[reg]; in aspeed_sli_read()
43 if (reg >= ARRAY_SIZE(s->regs)) { in aspeed_sli_write()
45 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", in aspeed_sli_write()
51 s->regs[reg] = data; in aspeed_sli_write()
[all …]
H A Dunimp.c27 s->name, size, s->offset_fmt_width, offset); in unimp_read()
39 s->name, size, s->offset_fmt_width, offset, size << 1, value); in unimp_write()
47 .valid.min_access_size = 1,
48 .valid.max_access_size = 8,
56 if (s->size == 0) { in unimp_realize()
61 if (s->name == NULL) { in unimp_realize()
66 s->offset_fmt_width = DIV_ROUND_UP(64 - clz64(s->size - 1), 4); in unimp_realize()
68 memory_region_init_io(&s->iomem, OBJECT(s), &unimp_ops, s, in unimp_realize()
69 s->name, s->size); in unimp_realize()
70 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); in unimp_realize()
[all …]
H A Daspeed_xdma.c6 * SPDX-License-Identifier: GPL-2.0-or-later
11 #include "qemu/error-report.h"
56 val = xdma->regs[TO_REG(addr)]; in aspeed_xdma_read()
74 if (addr == axc->cmdq_endp) { in aspeed_xdma_write()
75 xdma->regs[TO_REG(addr)] = val32 & XDMA_BMC_CMDQ_W_MASK; in aspeed_xdma_write()
76 } else if (addr == axc->cmdq_wrp) { in aspeed_xdma_write()
78 xdma->regs[idx] = val32 & XDMA_BMC_CMDQ_W_MASK; in aspeed_xdma_write()
79 xdma->regs[TO_REG(axc->cmdq_rdp)] = xdma->regs[idx]; in aspeed_xdma_write()
83 if (xdma->bmc_cmdq_readp_set) { in aspeed_xdma_write()
84 xdma->bmc_cmdq_readp_set = 0; in aspeed_xdma_write()
[all …]
/openbmc/qemu/hw/adc/
H A Daspeed_adc.c4 * Copyright 2017-2021 IBM Corp.
8 * SPDX-License-Identifier: GPL-2.0-or-later
15 #include "hw/qdev-properties.h"
34 #define ASPEED_ADC_L_MASK ((1 << 10) - 1)
38 #define LOWER_CHANNEL_MASK ((1 << 10) - 1)
72 reg < DATA_CHANNEL_1_AND_0 + s->nr_channels / 2); in breaks_threshold()
74 int a_bounds_reg = BOUNDS_CHANNEL_0 + (reg - DATA_CHANNEL_1_AND_0) * 2; in breaks_threshold()
76 uint32_t a_and_b = s->regs[reg]; in breaks_threshold()
77 uint32_t a_bounds = s->regs[a_bounds_reg]; in breaks_threshold()
78 uint32_t b_bounds = s->regs[b_bounds_reg]; in breaks_threshold()
[all …]
/openbmc/qemu/hw/usb/
H A Dhcd-ehci-sysbus.c19 #include "hw/qdev-properties.h"
20 #include "hw/usb/hcd-ehci.h"
24 .name = "ehci-sysbus",
35 DEFINE_PROP_BOOL("companion-enable", EHCISysBusState, ehci.companion_enable,
43 EHCIState *s = &i->ehci; in usb_ehci_sysbus_realize()
46 sysbus_init_irq(d, &s->irq); in usb_ehci_sysbus_realize()
53 EHCIState *s = &i->ehci; in usb_ehci_sysbus_reset()
63 EHCIState *s = &i->ehci; in ehci_sysbus_init()
65 s->capsbase = sec->capsbase; in ehci_sysbus_init()
66 s->opregbase = sec->opregbase; in ehci_sysbus_init()
[all …]
H A Dhcd-uhci-sysbus.c
/openbmc/qemu/hw/ppc/
H A Dpnv_homer.c25 #include "hw/qdev-core.h"
26 #include "hw/qdev-properties.h"
52 val = homer->base; in pnv_homer_power8_pba_read()
55 val = (hmrc->size - 1) & 0x300000; in pnv_homer_power8_pba_read()
61 val = (PNV_OCC_COMMON_AREA_SIZE - 1) & 0x700000; in pnv_homer_power8_pba_read()
80 .valid.min_access_size = 8,
81 .valid.max_access_size = 8,
96 homer->get_base = pnv_homer_power8_get_base; in pnv_homer_power8_class_init()
97 homer->size = PNV_HOMER_SIZE; in pnv_homer_power8_class_init()
98 homer->pba_size = PNV_XSCOM_PBA_SIZE; in pnv_homer_power8_class_init()
[all …]
H A Dpnv_core.c32 #include "hw/qdev-properties.h"
38 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX); in pnv_core_cpu_typename()
48 CPUPPCState *env = &cpu->env; in pnv_core_cpu_reset()
49 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); in pnv_core_cpu_reset()
57 env->gpr[3] = PNV_FDT_ADDR; in pnv_core_cpu_reset()
58 env->nip = 0x10; in pnv_core_cpu_reset()
59 env->msr |= MSR_HVB; /* Hypervisor mode */ in pnv_core_cpu_reset()
60 env->spr[SPR_HRMOR] = pc->hrmor; in pnv_core_cpu_reset()
61 if (pc->big_core) { in pnv_core_cpu_reset()
63 env->spr[SPR_PVR] &= ~PPC_BIT(51); in pnv_core_cpu_reset()
[all …]
H A Dpnv_n1_chiplet.c6 * SPDX-License-Identifier: GPL-2.0-or-later
11 #include "hw/qdev-properties.h"
38 val = n1_chiplet->eq[0].hp_mode2_curr; in pnv_n1_chiplet_pb_scom_eq_read()
55 n1_chiplet->eq[0].hp_mode2_curr = val; in pnv_n1_chiplet_pb_scom_eq_write()
66 .valid.min_access_size = 8,
67 .valid.max_access_size = 8,
82 val = n1_chiplet->es[3].mode; in pnv_n1_chiplet_pb_scom_es_read()
99 n1_chiplet->es[3].mode = val; in pnv_n1_chiplet_pb_scom_es_write()
110 .valid.min_access_size = 8,
111 .valid.max_access_size = 8,
[all …]
H A Dpnv_sbe.c25 #include "hw/qdev-properties.h"
39 * Reg 0 - 3 : Host to send command packets to SBE
40 * Reg 4 - 7 : SBE to send response packets to Host
121 .valid.min_access_size = 8,
122 .valid.max_access_size = 8,
131 sbe->host_doorbell = val; in pnv_sbe_set_host_doorbell()
134 qemu_set_irq(sbe->psi_irq, !!val); in pnv_sbe_set_host_doorbell()
158 * - xx : command class
159 * - yy : command
202 pnv_sbe_set_host_doorbell(sbe, sbe->host_doorbell | SBE_HOST_TIMER_EXPIRY); in sbe_timer()
[all …]
/openbmc/qemu/hw/display/
H A Dvga-mmio.c29 #include "hw/qdev-properties.h"
58 return vga_ioport_read(&s->vga, addr >> s->it_shift) & in vga_mm_read()
67 vga_ioport_write(&s->vga, addr >> s->it_shift, in vga_mm_write()
74 .valid.min_access_size = 1,
75 .valid.max_access_size = 4,
85 vga_common_reset(&s->vga); in vga_mmio_reset()
93 memory_region_init_io(&s->iomem, OBJECT(dev), &vga_mm_ctrl_ops, s, in vga_mmio_realizefn()
94 "vga-mmio", 0x100000); in vga_mmio_realizefn()
95 memory_region_set_flush_coalesced(&s->iomem); in vga_mmio_realizefn()
96 sysbus_init_mmio(sbd, &s->iomem); in vga_mmio_realizefn()
[all …]
H A Dvga-pci.c4 * see docs/specs/standard-vga.rst for virtual hardware specs.
29 #include "hw/qdev-properties.h"
57 #define TYPE_PCI_VGA "pci-vga"
113 .valid.min_access_size = 1,
114 .valid.max_access_size = 4,
143 .valid.min_access_size = 1,
144 .valid.max_access_size = 4,
158 return s->big_endian_fb ? in pci_vga_qext_read()
173 s->big_endian_fb = true; in pci_vga_qext_write()
176 s->big_endian_fb = false; in pci_vga_qext_write()
[all …]
/openbmc/qemu/hw/pci-host/
H A Darticia.c18 #include "hw/pci-host/articia.h"
45 uint32_t gpio; /* bits 0-7 in, 8-15 out, 16-23 direction (0 in, 1 out) */
54 return (s->gpio >> (addr * 8)) & 0xff; in articia_gpio_read()
68 if ((s->gpio & (0xff << sh)) != (val & 0xff) << sh) { in articia_gpio_write()
69 s->gpio &= ~(0xff << sh | 0xff); in articia_gpio_write()
70 s->gpio |= (val & 0xff) << sh; in articia_gpio_write()
71 s->gpio |= bitbang_i2c_set(&s->smbus, BITBANG_I2C_SDA, in articia_gpio_write()
72 s->gpio & BIT(16) ? in articia_gpio_write()
73 !!(s->gpio & BIT(8)) : 1); in articia_gpio_write()
74 if ((s->gpio & BIT(17))) { in articia_gpio_write()
[all …]
/openbmc/qemu/hw/intc/
H A Dloongson_ipi.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 #include "hw/qdev-properties.h"
16 if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) { in get_iocsr_as()
17 return &MIPS_CPU(cpu)->env.iocsr.as; in get_iocsr_as()
34 *index = cs->cpu_index; in loongson_cpu_by_arch_id()
49 .valid.min_access_size = 4,
50 .valid.max_access_size = 8,
63 lic->parent_realize(dev, &local_err); in loongson_ipi_realize()
69 if (sc->num_cpu == 0) { in loongson_ipi_realize()
70 error_setg(errp, "num-cpu must be at least 1"); in loongson_ipi_realize()
[all …]
/openbmc/qemu/hw/s390x/
H A Dccw-device.c8 * your option) any later version. See the COPYING file in the top-level
13 #include "ccw-device.h"
14 #include "hw/qdev-properties.h"
23 SubchDev *sch = dev->sch; in ccw_device_refill_ids()
27 dev->dev_id.cssid = sch->cssid; in ccw_device_refill_ids()
28 dev->dev_id.ssid = sch->ssid; in ccw_device_refill_ids()
29 dev->dev_id.devid = sch->devno; in ccw_device_refill_ids()
30 dev->dev_id.valid = true; in ccw_device_refill_ids()
32 dev->subch_id.cssid = sch->cssid; in ccw_device_refill_ids()
33 dev->subch_id.ssid = sch->ssid; in ccw_device_refill_ids()
[all …]
/openbmc/qemu/hw/tpm/
H A Dtpm_spapr.c12 * COPYING file in the top-level directory.
17 #include "qemu/error-report.h"
19 #include "hw/qdev-properties.h"
38 uint8_t valid; /* 0x80: cmd; 0xc0: init crq */ member
39 /* 0x81-0x83: CRQ message response */
50 /* msg types for valid = SPAPR_VTPM_VALID_INIT_CRQ */
54 /* msg types for valid = SPAPR_VTPM_VALID_CMD */
96 tpm_util_show_buffer(s->buffer, s->be_buffer_size, "To TPM"); in tpm_spapr_tpm_send()
98 s->state = SPAPR_VTPM_STATE_EXECUTION; in tpm_spapr_tpm_send()
99 s->cmd = (TPMBackendCmd) { in tpm_spapr_tpm_send()
[all …]
/openbmc/qemu/hw/char/
H A Dserial-mm.c4 * Copyright (c) 2003-2004 Fabrice Bellard
27 #include "hw/char/serial-mm.h"
28 #include "exec/cpu-common.h"
31 #include "hw/qdev-properties.h"
36 return serial_io_ops.read(&s->serial, addr >> s->regshift, 1); in serial_mm_read()
44 serial_io_ops.write(&s->serial, addr >> s->regshift, value, 1); in serial_mm_write()
52 .valid.max_access_size = 8,
59 .valid.max_access_size = 8,
66 .valid.max_access_size = 8,
74 SerialState *s = &smm->serial; in serial_mm_realize()
[all …]
H A Ddebugcon.c2 * QEMU Bochs-style debug console ("port E9") emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
30 #include "chardev/char-fe.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/qdev-properties-system.h"
36 #define TYPE_ISA_DEBUGCON_DEVICE "isa-debugcon"
66 qemu_chr_fe_write_all(&s->chr, &ch, 1); in debugcon_ioport_write()
78 return s->readback; in debugcon_ioport_read()
84 .valid.min_access_size = 1,
85 .valid.max_access_size = 1,
[all …]
/openbmc/qemu/hw/net/can/
H A Dctucan_pci.c34 #include "hw/qdev-properties.h"
86 ctucan_hardware_reset(&d->ctucan_state[i]); in ctucan_pci_reset()
100 tmp &= ((uint64_t)1 << (size << 3)) - 1; in ctucan_pci_id_cra_io_read()
122 s = &d->ctucan_state[core_num]; in ctucan_pci_cores_io_read()
138 s = &d->ctucan_state[core_num]; in ctucan_pci_cores_io_write()
149 .valid.min_access_size = 1,
150 .valid.max_access_size = 4,
159 .valid.min_access_size = 1,
160 .valid.max_access_size = 4,
169 pci_conf = pci_dev->config; in ctucan_pci_realize()
[all …]
/openbmc/qemu/hw/sd/
H A Daspeed_sdhci.c6 * SPDX-License-Identifier: GPL-2.0-or-later
11 #include "qemu/error-report.h"
16 #include "hw/qdev-properties.h"
45 val = extract64(sdhci->slots[0].capareg, 0, 32); in aspeed_sdhci_read()
48 val = extract64(sdhci->slots[0].capareg, 32, 32); in aspeed_sdhci_read()
51 val = extract64(sdhci->slots[0].maxcurr, 0, 32); in aspeed_sdhci_read()
54 val = extract64(sdhci->slots[1].capareg, 0, 32); in aspeed_sdhci_read()
57 val = extract64(sdhci->slots[1].capareg, 32, 32); in aspeed_sdhci_read()
60 val = extract64(sdhci->slots[1].maxcurr, 0, 32); in aspeed_sdhci_read()
64 val = sdhci->regs[TO_REG(addr)]; in aspeed_sdhci_read()
[all …]
/openbmc/qemu/hw/fsi/
H A Dcfam.c2 * SPDX-License-Identifier: GPL-2.0-or-later
17 #include "hw/qdev-properties.h"
24 /* Valid, slots, version, type, crc */
74 bus_cold_reset(BUS(&cfam->lbus)); in fsi_cfam_config_write()
85 .valid.max_access_size = 4,
86 .valid.min_access_size = 4,
116 object_initialize_child(obj, "scratchpad", &s->scratchpad, in fsi_cfam_instance_init()
126 memory_region_init_io(&cfam->mr, OBJECT(cfam), &fsi_cfam_unimplemented_ops, in fsi_cfam_realize()
129 qbus_init(&cfam->lbus, sizeof(cfam->lbus), TYPE_FSI_LBUS, DEVICE(cfam), in fsi_cfam_realize()
132 memory_region_init_io(&cfam->config_iomem, OBJECT(cfam), &cfam_config_ops, in fsi_cfam_realize()
[all …]

12345678910>>...18