| /openbmc/linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_link_enc_cfg.c | 29 #define DC_LOGGER dc->ctx->logger
40 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in is_dig_link_enc_stream()
41 link_enc = stream->ctx->dc->res_pool->link_encoders[i]; in is_dig_link_enc_stream()
46 if (link_enc && ((uint32_t)stream->link->connector_signal & link_enc->output_signals)) { in is_dig_link_enc_stream()
47 if (dc_is_dp_signal(stream->signal)) { in is_dig_link_enc_stream()
51 stream->ctx->dc->link_srv->dp_decide_link_settings(stream, &link_settings); in is_dig_link_enc_stream()
67 static struct link_enc_assignment get_assignment(struct dc *dc, int i) in get_assignment() argument
71 if (dc->current_state->res_ctx.link_enc_cfg_ctx.mode == LINK_ENC_CFG_TRANSIENT) in get_assignment()
72 assignment = dc->current_state->res_ctx.link_enc_cfg_ctx.transient_assignments[i]; in get_assignment()
74 assignment = dc->current_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i]; in get_assignment()
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| H A D | dc_vm_helper.c | 27 #include "dc.h"
31 struct vmid_usage vmids = vm_helper->hubp_vmid_usage[hubp_idx]; in vm_helper_mark_vmid_used()
37 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config) in dc_setup_system_context() argument
42 if (dc->hwss.init_sys_ctx) { in dc_setup_system_context()
43 num_vmids = dc->hwss.init_sys_ctx(dc->hwseq, dc, pa_config); in dc_setup_system_context()
45 /* Pre-init system aperture start/end for all HUBP instances (if not gating?) in dc_setup_system_context()
48 memcpy(&dc->vm_pa_config, pa_config, sizeof(struct dc_phy_addr_space_config)); in dc_setup_system_context()
49 dc->vm_pa_config.valid = true; in dc_setup_system_context()
50 dc_z10_save_init(dc); in dc_setup_system_context()
56 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid) in dc_setup_vm_context() argument
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 2 * Copyright 2019-2021 Advanced Micro Devices, Inc.
37 /* Based on: //vidip/dc/dcn3/doc/architecture/DCN3x_Display_Mode.xlsm#83 */
226 .valid = true,
234 .valid = true,
242 .valid = true,
250 .valid = true,
263 .valid = true,
271 .valid = true,
279 .valid = true,
287 .valid = true,
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| /openbmc/linux/Documentation/devicetree/bindings/power/supply/ |
| H A D | qcom,pm8941-charger.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/supply/qcom,pm8941-charger.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Switch-Mode Battery Charger and Boost
10 - Sebastian Reichel <sre@kernel.org>
15 - qcom,pm8226-charger
16 - qcom,pm8941-charger
23 - description: charge done
24 - description: charge fast mode
[all …]
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| /openbmc/qemu/hw/ppc/ |
| H A D | pnv_occ.c | 4 * Copyright (c) 2015-2017, IBM Corporation.
25 #include "hw/qdev-properties.h"
58 occ->occmisc = val; in pnv_occ_set_misc()
60 qemu_set_irq(occ->psi_irq, irq_state); in pnv_occ_set_misc()
72 val = occ->occmisc; in pnv_occ_power8_xscom_read()
89 pnv_occ_set_misc(occ, occ->occmisc & val); in pnv_occ_power8_xscom_write()
92 pnv_occ_set_misc(occ, occ->occmisc | val); in pnv_occ_power8_xscom_write()
108 * occ-sensor sanity check that asserts the sensor in pnv_occ_common_area_read()
148 .valid.min_access_size = 8,
149 .valid.max_access_size = 8,
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| H A D | pnv_core.c | 32 #include "hw/qdev-properties.h"
38 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX); in pnv_core_cpu_typename()
48 CPUPPCState *env = &cpu->env; in pnv_core_cpu_reset()
49 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); in pnv_core_cpu_reset()
57 env->gpr[3] = PNV_FDT_ADDR; in pnv_core_cpu_reset()
58 env->nip = 0x10; in pnv_core_cpu_reset()
59 env->msr |= MSR_HVB; /* Hypervisor mode */ in pnv_core_cpu_reset()
60 env->spr[SPR_HRMOR] = pc->hrmor; in pnv_core_cpu_reset()
61 if (pc->big_core) { in pnv_core_cpu_reset()
63 env->spr[SPR_PVR] &= ~PPC_BIT(51); in pnv_core_cpu_reset()
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| H A D | pnv_homer.c | 25 #include "hw/qdev-core.h"
26 #include "hw/qdev-properties.h"
38 for (i = 0; i <= homer->chip->nr_cores; i++) { in core_max_array()
39 if (addr == (hmrc->core_max_base + i)) { in core_max_array()
113 .valid.min_access_size = 1,
114 .valid.max_access_size = 8,
134 PnvChip *chip = homer->chip; in pnv_homer_power8_pba_read()
143 val = (PNV_HOMER_SIZE - 1) & 0x300000; in pnv_homer_power8_pba_read()
149 val = (PNV_OCC_COMMON_AREA_SIZE - 1) & 0x700000; in pnv_homer_power8_pba_read()
168 .valid.min_access_size = 8,
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| /openbmc/qemu/hw/adc/ |
| H A D | aspeed_adc.c | 4 * Copyright 2017-2021 IBM Corp.
8 * SPDX-License-Identifier: GPL-2.0-or-later
15 #include "hw/qdev-properties.h"
34 #define ASPEED_ADC_L_MASK ((1 << 10) - 1)
38 #define LOWER_CHANNEL_MASK ((1 << 10) - 1)
72 reg < DATA_CHANNEL_1_AND_0 + s->nr_channels / 2); in breaks_threshold()
74 int a_bounds_reg = BOUNDS_CHANNEL_0 + (reg - DATA_CHANNEL_1_AND_0) * 2; in breaks_threshold()
76 uint32_t a_and_b = s->regs[reg]; in breaks_threshold()
77 uint32_t a_bounds = s->regs[a_bounds_reg]; in breaks_threshold()
78 uint32_t b_bounds = s->regs[b_bounds_reg]; in breaks_threshold()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.c | 70 struct dc *dc, in dcn316_get_active_display_cnt_wa() argument
77 for (i = 0; i < context->stream_count; i++) { in dcn316_get_active_display_cnt_wa()
78 const struct dc_stream_state *stream = context->streams[i]; in dcn316_get_active_display_cnt_wa()
80 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || in dcn316_get_active_display_cnt_wa()
81 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || in dcn316_get_active_display_cnt_wa()
82 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) in dcn316_get_active_display_cnt_wa()
86 for (i = 0; i < dc->link_count; i++) { in dcn316_get_active_display_cnt_wa()
87 const struct dc_link *link = dc->links[i]; in dcn316_get_active_display_cnt_wa()
90 if (link->link_enc && link->link_enc->funcs->is_dig_enabled && in dcn316_get_active_display_cnt_wa()
91 link->link_enc->funcs->is_dig_enabled(link->link_enc)) in dcn316_get_active_display_cnt_wa()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.c | 55 clk_mgr->base.base.ctx->logger
76 struct dc *dc, in dcn31_get_active_display_cnt_wa() argument
83 for (i = 0; i < context->stream_count; i++) { in dcn31_get_active_display_cnt_wa()
84 const struct dc_stream_state *stream = context->streams[i]; in dcn31_get_active_display_cnt_wa()
86 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || in dcn31_get_active_display_cnt_wa()
87 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || in dcn31_get_active_display_cnt_wa()
88 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) in dcn31_get_active_display_cnt_wa()
92 if (dc_is_dp_signal(stream->signal) && !stream->dpms_off) in dcn31_get_active_display_cnt_wa()
97 for (i = 0; i < dc->link_count; i++) { in dcn31_get_active_display_cnt_wa()
98 const struct dc_link *link = dc->links[i]; in dcn31_get_active_display_cnt_wa()
[all …]
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| /openbmc/qemu/hw/watchdog/ |
| H A D | sbsa_gwdt.c | 14 * option) any later version. See the COPYING file in the top-level directory.
21 #include "hw/qdev-properties.h"
29 .name = "sbsa-gwdt",
59 ret = s->id; in sbsa_gwdt_rread()
75 ret = s->wcs; in sbsa_gwdt_read()
78 ret = s->worl; in sbsa_gwdt_read()
81 ret = s->woru; in sbsa_gwdt_read()
84 ret = s->wcvl; in sbsa_gwdt_read()
87 ret = s->wcvu; in sbsa_gwdt_read()
90 ret = s->id; in sbsa_gwdt_read()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 1 // SPDX-License-Identifier: MIT
77 * the DC FPU interface functions, we introduce a helper that checks if the
773 .valid = true,
781 .valid = true,
789 .valid = true,
797 .valid = true,
810 .valid = true,
818 .valid = true,
826 .valid = true,
834 .valid = true,
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| /openbmc/qemu/hw/usb/ |
| H A D | hcd-ehci-sysbus.c | 19 #include "hw/qdev-properties.h"
20 #include "hw/usb/hcd-ehci.h"
24 .name = "ehci-sysbus",
35 DEFINE_PROP_BOOL("companion-enable", EHCISysBusState, ehci.companion_enable,
44 EHCIState *s = &i->ehci; in usb_ehci_sysbus_realize()
47 sysbus_init_irq(d, &s->irq); in usb_ehci_sysbus_realize()
54 EHCIState *s = &i->ehci; in usb_ehci_sysbus_reset()
64 EHCIState *s = &i->ehci; in ehci_sysbus_init()
66 s->capsbase = sec->capsbase; in ehci_sysbus_init()
67 s->opregbase = sec->opregbase; in ehci_sysbus_init()
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| H A D | hcd-uhci-sysbus.c | 23 #include "hw/usb/uhci-regs.h"
31 #include "hw/qdev-dma.h"
32 #include "hw/qdev-properties.h"
34 #include "hcd-uhci.h"
35 #include "hcd-uhci-sysbus.h"
45 UHCIState *uhci = &s->uhci; in uhci_sysbus_realize()
49 uhci->masterbus = s->masterbus; in uhci_sysbus_realize()
50 uhci->firstport = s->firstport; in uhci_sysbus_realize()
51 uhci->maxframes = s->maxframes; in uhci_sysbus_realize()
52 uhci->frame_bandwidth = s->frame_bandwidth; in uhci_sysbus_realize()
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| /openbmc/linux/Documentation/devicetree/bindings/iio/dac/ |
| H A D | adi,ad5755.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD5755 Multi-Channel DAC
10 - Sean Nyekjaer <sean.nyekjaer@prevas.dk>
15 - adi,ad5755
16 - adi,ad5755-1
17 - adi,ad5757
18 - adi,ad5735
19 - adi,ad5737
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| /openbmc/qemu/hw/misc/ |
| H A D | bcm2835_thermal.c | 4 * Copyright (C) 2019 Philippe Mathieu-Daudé <f4bug@amsat.org>
6 * SPDX-License-Identifier: GPL-2.0-or-later
29 FIELD(STAT, VALID, 10, 1)
33 #define THERMAL_COEFF (-0.538f)
37 return (temp_C - THERMAL_OFFSET_C) / THERMAL_COEFF; in bcm2835_thermal_temp2adc()
47 val = s->ctl; in bcm2835_thermal_read()
51 val = FIELD_DP32(bcm2835_thermal_temp2adc(25), STAT, VALID, true); in bcm2835_thermal_read()
67 s->ctl = value; in bcm2835_thermal_write()
85 .valid.min_access_size = 4,
86 .valid.max_access_size = 4,
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| H A D | aspeed_scu.c | 9 * the COPYING file in the top-level directory.
14 #include "hw/qdev-properties.h"
20 #include "qemu/guest-random.h"
259 return ASPEED_SCU_GET_CLASS(s)->get_apb(s); in aspeed_scu_get_apb_freq()
265 uint32_t hpll = asc->calc_hpll(s, s->regs[HPLL_PARAM]); in aspeed_2400_scu_get_apb_freq()
267 return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1) in aspeed_2400_scu_get_apb_freq()
268 / asc->apb_divider; in aspeed_2400_scu_get_apb_freq()
274 uint32_t hpll = asc->calc_hpll(s, s->regs[AST2600_HPLL_PARAM]); in aspeed_2600_scu_get_apb_freq()
276 return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[AST2600_CLK_SEL]) + 1) in aspeed_2600_scu_get_apb_freq()
277 / asc->apb_divider; in aspeed_2600_scu_get_apb_freq()
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| H A D | debugexit.c | 12 #include "hw/qdev-properties.h"
17 #define TYPE_ISA_DEBUG_EXIT_DEVICE "isa-debug-exit"
43 .valid.min_access_size = 1,
44 .valid.max_access_size = 4,
53 memory_region_init_io(&isa->io, OBJECT(dev), &debug_exit_ops, isa, in debug_exit_realizefn()
54 TYPE_ISA_DEBUG_EXIT_DEVICE, isa->iosize); in debug_exit_realizefn()
56 isa->iobase, &isa->io); in debug_exit_realizefn()
67 DeviceClass *dc = DEVICE_CLASS(klass); in debug_exit_class_initfn() local
69 dc->realize = debug_exit_realizefn; in debug_exit_class_initfn()
70 device_class_set_props(dc, debug_exit_properties); in debug_exit_class_initfn()
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| H A D | aspeed_sli.c | 6 * SPDX-License-Identifier: GPL-2.0-or-later
11 #include "qemu/error-report.h"
12 #include "hw/qdev-properties.h"
26 if (reg >= ARRAY_SIZE(s->regs)) { in aspeed_sli_read()
28 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", in aspeed_sli_read()
33 trace_aspeed_sli_read(addr, size, s->regs[reg]); in aspeed_sli_read()
34 return s->regs[reg]; in aspeed_sli_read()
43 if (reg >= ARRAY_SIZE(s->regs)) { in aspeed_sli_write()
45 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", in aspeed_sli_write()
51 s->regs[reg] = data; in aspeed_sli_write()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | dcn30_fpu.c | 2 * Copyright 2020-2021 Advanced Micro Devices, Inc.
37 optc1->tg_regs->reg
40 optc1->base.ctx
44 optc1->tg_shift->field_name, optc1->tg_mask->field_name
193 * VOTAL_MAX - VTOTAL_MIN = 1 in optc3_fpu_set_vrr_m_const()
201 * of lines in a frame - 1'. in optc3_fpu_set_vrr_m_const()
213 optc->funcs->set_vtotal_min_max(optc, 0, 0); in optc3_fpu_set_vrr_m_const()
223 ratio = vtotal_max - vtotal_avg; in optc3_fpu_set_vrr_m_const()
224 modulo = 65536.0 * 65536.0 - 1.0; /* 2^32 - 1 */ in optc3_fpu_set_vrr_m_const()
252 optc->funcs->set_vtotal_min_max(optc, vtotal_min, vtotal_max); in optc3_fpu_set_vrr_m_const()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_clk_mgr.c | 47 clk_mgr->base.base.ctx->logger
58 struct dc *dc, in dcn315_get_active_display_cnt_wa() argument
65 for (i = 0; i < context->stream_count; i++) { in dcn315_get_active_display_cnt_wa()
66 const struct dc_stream_state *stream = context->streams[i]; in dcn315_get_active_display_cnt_wa()
68 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || in dcn315_get_active_display_cnt_wa()
69 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || in dcn315_get_active_display_cnt_wa()
70 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) in dcn315_get_active_display_cnt_wa()
74 for (i = 0; i < dc->link_count; i++) { in dcn315_get_active_display_cnt_wa()
75 const struct dc_link *link = dc->links[i]; in dcn315_get_active_display_cnt_wa()
78 if (link->link_enc && link->link_enc->funcs->is_dig_enabled && in dcn315_get_active_display_cnt_wa()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.c | 1 // SPDX-License-Identifier: MIT
58 clk_mgr->base.base.ctx->logger
97 struct dc *dc, in dcn314_get_active_display_cnt_wa() argument
104 for (i = 0; i < context->stream_count; i++) { in dcn314_get_active_display_cnt_wa()
105 const struct dc_stream_state *stream = context->streams[i]; in dcn314_get_active_display_cnt_wa()
107 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || in dcn314_get_active_display_cnt_wa()
108 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || in dcn314_get_active_display_cnt_wa()
109 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) in dcn314_get_active_display_cnt_wa()
113 if (dc_is_dp_signal(stream->signal) && !stream->dpms_off) in dcn314_get_active_display_cnt_wa()
118 for (i = 0; i < dc->link_count; i++) { in dcn314_get_active_display_cnt_wa()
[all …]
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| /openbmc/qemu/hw/display/ |
| H A D | vga-pci.c | 4 * see docs/specs/standard-vga.rst for virtual hardware specs.
29 #include "hw/qdev-properties.h"
57 #define TYPE_PCI_VGA "pci-vga"
113 .valid.min_access_size = 1,
114 .valid.max_access_size = 4,
143 .valid.min_access_size = 1,
144 .valid.max_access_size = 4,
158 return s->big_endian_fb ? in pci_vga_qext_read()
173 s->big_endian_fb = true; in pci_vga_qext_write()
176 s->big_endian_fb = false; in pci_vga_qext_write()
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| H A D | vga-mmio.c | 29 #include "hw/qdev-properties.h"
58 return vga_ioport_read(&s->vga, addr >> s->it_shift) & in vga_mm_read()
67 vga_ioport_write(&s->vga, addr >> s->it_shift, in vga_mm_write()
74 .valid.min_access_size = 1,
75 .valid.max_access_size = 4,
85 vga_common_reset(&s->vga); in vga_mmio_reset()
93 memory_region_init_io(&s->iomem, OBJECT(dev), &vga_mm_ctrl_ops, s, in vga_mmio_realizefn()
94 "vga-mmio", 0x100000); in vga_mmio_realizefn()
95 memory_region_set_flush_coalesced(&s->iomem); in vga_mmio_realizefn()
96 sysbus_init_mmio(sbd, &s->iomem); in vga_mmio_realizefn()
[all …]
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| /openbmc/qemu/hw/pci-host/ |
| H A D | articia.c | 18 #include "hw/pci-host/articia.h"
45 uint32_t gpio; /* bits 0-7 in, 8-15 out, 16-23 direction (0 in, 1 out) */
54 return (s->gpio >> (addr * 8)) & 0xff; in articia_gpio_read()
68 if ((s->gpio & (0xff << sh)) != (val & 0xff) << sh) { in articia_gpio_write()
69 s->gpio &= ~(0xff << sh | 0xff); in articia_gpio_write()
70 s->gpio |= (val & 0xff) << sh; in articia_gpio_write()
71 s->gpio |= bitbang_i2c_set(&s->smbus, BITBANG_I2C_SDA, in articia_gpio_write()
72 s->gpio & BIT(16) ? in articia_gpio_write()
73 !!(s->gpio & BIT(8)) : 1); in articia_gpio_write()
74 if ((s->gpio & BIT(17))) { in articia_gpio_write()
[all …]
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