History log of /openbmc/qemu/hw/usb/hcd-uhci-sysbus.c (Results 1 – 2 of 2)
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Revision tags: v9.2.0, v9.1.2
# a829d749 12-Nov-2024 Guenter Roeck <linux@roeck-us.net>

usb/uhci: Add aspeed specific read and write functions

Aspeed uses non-standard UHCI register addresses. On top of that,
registers are 32 bit wide instead of 16 bit.

Map Aspeed UHCI addresses to st

usb/uhci: Add aspeed specific read and write functions

Aspeed uses non-standard UHCI register addresses. On top of that,
registers are 32 bit wide instead of 16 bit.

Map Aspeed UHCI addresses to standard UHCI addresses and where needed
combine/split 32 bit accesses to solve the problem.

In addition to that, Aspeed SoCs starting with AST2600 support and use EHCI
companion mode on the second EHCI interface. Support this by moving the
property initialization to the Aspeed class initialization code. Since the
USB ports are part of the SoC and always present, set user_creatable to
false for the Aspeed UHCI controller.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>

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# 83698261 12-Nov-2024 Guenter Roeck <linux@roeck-us.net>

usb/uhci: Add support for usb-uhci-sysbus

Signed-off-by: Guenter Roeck <linux@roeck-us.net>