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/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/State/Boot/
H A DPostCode.interface.yaml2 Monitor Post code coming and buffer all of them based on boot cycle into
20 Method to get the cached post codes of the indicated boot cycle with
26 Index indicates which boot cycle of post codes is requested. 1
27 is for the most recent boot cycle. CurrentBootCycleCount is for
28 the oldest boot cycle.
36 Method to get the cached post codes of the indicated boot cycle.
41 Index indicates which boot cycle of post codes is requested. 1
42 is for the most recent boot cycle. CurrentBootCycleCount is for
43 the oldest boot cycle.
48 An array of post codes of one boot cycle.
/openbmc/openbmc/meta-facebook/meta-santabarbara/recipes-phosphor/state/phosphor-state-manager/
H A Dchassis-powercycle6 #Sled cycle
7 echo "Starting Chassis Power Cycle"
9 chassis-power-cycle-ltc4287() {
42 chassis-power-cycle-xdp711() {
60 chassis-power-cycle()
63 # run main source power cycle if 47-000f exist
64 chassis-power-cycle-ltc4287
67 # run 2nd source power cycle
68 chassis-power-cycle-xdp711
79 echo "Starting Chassis Power Cycle"
[all …]
/openbmc/openbmc/meta-facebook/meta-yosemite5/recipes-phosphor/state/phosphor-state-manager/
H A Dchassis-powercycle6 #Sled cycle
7 echo "Starting Chassis Power Cycle"
9 chassis-power-cycle() {
19 blade-power-cycle() {
33 echo "Starting Chassis AC Cycle"
34 chassis-power-cycle
36 echo "Starting AC Cycle"
37 blade-power-cycle
/openbmc/openbmc-test-automation/extended/
H A Dtest_bmc_reset_loop.robot2 Documentation Power cycle loop. This is to test where network service
3 ... becomes unavailable during AC-Cycle stress test.
24 ${ERROR_REGEX} SEGV|core-dump|FAILURE|Failed to start|Found ordering cycle
28 Run Multiple Power Cycle
36 Repeat Keyword ${LOOP_COUNT} times Power Cycle System Via PDU
46 Repeat Keyword ${LOOP_COUNT} times BMC Redfish Reset Cycle
56 Repeat Keyword ${LOOP_COUNT} times BMC Reboot Cycle
66 Repeat Keyword ${LOOP_COUNT} times BMC Redfish Reset Runtime Cycle
70 Power Cycle System Via PDU
71 [Documentation] Power cycle system and wait for BMC to reach Ready state.
[all …]
/openbmc/openbmc/meta-facebook/meta-minerva/recipes-phosphor/state/phosphor-state-manager/
H A Dchassis-powercycle6 # Minerva CMM Sled Power Cycle and Chassis Power Cycle
8 cmm-hsc-power-cycle() {
69 # CMM Sled Power Cycle
72 echo "Staring CMM Sled Power Cycle"
73 cmm-hsc-power-cycle
74 # CMM Chassis Power Cycle
77 echo "Staring CMM Chassis Power Cycle"
82 cmm-hsc-power-cycle
84 echo "Invalid CMM Cycle"
/openbmc/openbmc/meta-facebook/meta-harma/recipes-phosphor/state/phosphor-state-manager/
H A Dchassis-powercycle6 #Sled cycle
7 echo "Starting Chassis Power Cycle"
9 chassis-power-cycle() {
37 aegis-power-cycle() {
47 echo "Starting Chassis Power Cycle"
54 # the AC cycle, ensuring that the write operation completes reliably.
57 chassis-power-cycle
61 echo "Starting Aegis Power Cycle"
62 aegis-power-cycle
/openbmc/openbmc/meta-fii/meta-kudo/recipes-kudo/hotswap-power-cycle/
H A Dhotswap-power-cycle.bb1 SUMMARY = "Power Cycle by Hotswap Controller"
2 DESCRIPTION = "Power Cycle by Hotswap Controller Daemon"
13 SRC_URI += " file://hotswap-power-cycle.service"
17 …install -m 0644 ${UNPACKDIR}/hotswap-power-cycle.service ${D}${systemd_unitdir}/system/hotswap-pow…
21 SYSTEMD_SERVICE:${PN} = " hotswap-power-cycle.service"
/openbmc/openbmc/meta-facebook/meta-anacapa/recipes-phosphor/state/phosphor-state-manager/
H A Dchassis-powercycle6 #Sled cycle
7 echo "Starting Chassis Power Cycle"
9 chassis-power-cycle() {
20 echo "Starting Chassis Power Cycle"
21 chassis-power-cycle
/openbmc/openbmc/meta-facebook/meta-ventura/recipes-phosphor/state/phosphor-state-manager/
H A Dchassis-powercycle3 # Ventura RMC Sled Power Cycle
5 rmc-hsc-power-cycle() {
36 # RMC Sled Power Cycle
39 echo "Staring RMC Sled Power Cycle"
40 rmc-hsc-power-cycle
42 echo "Invalid RMC Cycle"
/openbmc/openbmc/meta-quanta/meta-olympus-nuvoton/recipes-olympus-nuvoton/hotswap-power-cycle/
H A Dadm1278-hotswap-power-cycle.bb1 SUMMARY = "Power Cycle by Hotswap Controller"
2 DESCRIPTION = "Power Cycle by Hotswap Controller Daemon"
12 SRC_URI = " file://hotswap-power-cycle.service"
16 install -m 0644 ${UNPACKDIR}/hotswap-power-cycle.service ${D}${systemd_system_unitdir}
20 SYSTEMD_SERVICE:${PN} = "hotswap-power-cycle.service"
/openbmc/openbmc/meta-facebook/meta-yosemite4/recipes-phosphor/state/phosphor-state-manager/
H A Dchassis-powercycle24 echo "Failed to check management board fru info, sled cycle keep default setting"
43 echo "Do 12V cycle disable i3c hub"
115 chassis-power-cycle()
170 # Check chassis status after doing 12V cycle
195 msg="Chassis$CHASSIS_ID AC power cycle failed, Chassis$CHASSIS_ID is AC power off"
208 sled-cycle()
210 # Remount file system as read-only before doing sled cycle
231 msg="Execute sled cycle"
234 echo "Starting sled cycle..."
235 if ! sled-cycle
[all …]
H A Dhost-powercycle25 msg="Execute host$CHASSIS_ID DC power cycle"
31 msg="Wait power control flock release for host$CHASSIS_ID DC cycle"
41 # Current power is ON, cycle do OFF to ON. If current power is OFF then do ON
60 msg="Host$CHASSIS_ID DC power cycle failed, fail to set host$CHASSIS_ID DC power off"
76 msg="Host$CHASSIS_ID DC power cycle failed, fail to set host$CHASSIS_ID DC power on"
89 msg="Host$1 DC power cycle success"
/openbmc/openbmc/meta-facebook/meta-yosemite4/recipes-phosphor/chassis/obmc-phosphor-buttons/
H A Dgpio_defs.json14 "action": "chassis-cycle"
33 "action": "chassis-cycle"
52 "action": "chassis-cycle"
71 "action": "chassis-cycle"
90 "action": "chassis-cycle"
109 "action": "chassis-cycle"
128 "action": "chassis-cycle"
147 "action": "chassis-cycle"
/openbmc/pldm/oem/meta/libpldmresponder/
H A Dfile_io_type_power_control.hpp12 * to handle incoming sled cycle request from Hosts
31 * "SLED_CYCLE, 12V-CYCLE and DC-cycle" to let
34 * - 0x00: Sled-cycle
35 * - 0x01: Slot 12V-cycle
36 * - 0x02: Slot DC-cycle
/openbmc/openbmc-test-automation/data/boot_lists/
H A DPDU_reboot3 PDU AC Cycle (run)
4 PDU AC Cycle (run) (mfg)
5 PDU AC Cycle (off)
6 PDU AC Cycle (off) (mfg)
H A DAll37 PDU AC Cycle (run)
38 PDU AC Cycle (run) (mfg)
39 PDU AC Cycle (off)
40 PDU AC Cycle (off) (mfg)
57 IPMI Power Cycle
58 IPMI Power Cycle (mfg)
H A DOBMC_reboot15 PDU AC Cycle (run)
16 PDU AC Cycle (run) (mfg)
17 PDU AC Cycle (off)
18 PDU AC Cycle (off) (mfg)
/openbmc/qemu/tests/qapi-schema/
H A Dinclude-cycle.err1 In file included from include-cycle.json:1:
2 In file included from include-cycle-b.json:1:
3 include-cycle-c.json:1: inclusion loop for include-cycle.json
/openbmc/openbmc/meta-quanta/meta-gbs/recipes-gbs/hotswap-power-cycle/
H A Dgbs-hotswap-power-cycle.bb1 SUMMARY = "Power Cycle by Hotswap Controller"
2 DESCRIPTION = "Power Cycle by Hotswap Controller Daemon"
13 SRC_URI = " file://hotswap-power-cycle.service \
19 install -m 0644 ${UNPACKDIR}/hotswap-power-cycle.service ${D}${systemd_system_unitdir}
26 SYSTEMD_SERVICE:${PN} = "hotswap-power-cycle.service"
/openbmc/openbmc/meta-facebook/meta-bletchley/recipes-phosphor/state/phosphor-state-manager/
H A Dchassis-powercycle4 echo "Enter chassis-cycle"
5 /usr/sbin/power-ctrl chassis-cycle
7 echo "Enter sled$1 cycle"
8 /usr/sbin/power-ctrl "sled$1" cycle
/openbmc/u-boot/drivers/pwm/
H A DKconfig6 control over the duty cycle (high and low time) of the signal. This
17 supports a programmable period and duty cycle. A 32-bit counter is
26 programmable period and duty cycle. A 32-bit counter is used.
43 four channels with a programmable period and duty cycle. Only a
44 32KHz clock is supported by the driver but the duty cycle is
52 programmable period and duty cycle. A 16-bit counter is used.
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsys_proto.h22 * Data RAM setup latency: 1 cycle in configure_l2ctlr()
23 * Tag RAM write latency: 1 cycle in configure_l2ctlr()
24 * Tag RAM read latency: 1 cycle in configure_l2ctlr()
25 * Tag RAM setup latency: 1 cycle in configure_l2ctlr()
/openbmc/u-boot/arch/mips/mach-ath79/ar934x/
H A Dddr.c42 u32 reg, cycle, ctl; in ar934x_ddr_init() local
51 cycle = 0xffff; in ar934x_ddr_init()
57 cycle = 0xff; in ar934x_ddr_init()
59 cycle = 0xffff; in ar934x_ddr_init()
63 cycle = 0xffff; /* DDR2 16bit */ in ar934x_ddr_init()
80 cycle = 0xffffffff; in ar934x_ddr_init()
147 writel(cycle, ddr_regs + AR71XX_DDR_REG_RD_CYCLE); in ar934x_ddr_init()
/openbmc/qemu/hw/riscv/
H A Driscv-iommu-hpm.c27 /* For now we assume IOMMU HPM frequency to be 1GHz so 1-cycle is of 1-ns. */
35 const uint64_t cycle = riscv_iommu_reg_get64( in riscv_iommu_hpmcycle_read() local
42 trace_riscv_iommu_hpm_read(cycle, inhibit, ctr_prev, ctr_val); in riscv_iommu_hpmcycle_read()
51 (cycle & RISCV_IOMMU_IOHPMCYCLES_OVF); in riscv_iommu_hpmcycle_read()
55 (cycle & RISCV_IOMMU_IOHPMCYCLES_OVF); in riscv_iommu_hpmcycle_read()
71 * Generate interrupt only if OF bit is clear. +1 to offset the cycle in hpm_incr_ctr()
174 /* Timer callback for cycle counter overflow. */
221 * We are using INT64_MAX here instead to UINT64_MAX because cycle counter in hpm_setup_timer()
240 /* Updates the internal cycle counter state when iocntinh:CY is changed. */
255 * Cycle counter is enabled. Just start the timer again and update in riscv_iommu_process_iocntinh_cy()
[all …]
/openbmc/openbmc/meta-openembedded/meta-webserver/recipes-httpd/nginx/files/
H A Dnginx-fix-pidfile.patch31 if (ngx_init_signals(cycle->log) != NGX_OK) {
39 - if (ngx_daemon(cycle->log) != NGX_OK) {
40 + child_pid = ngx_daemon(cycle->log);
49 - if (ngx_create_pidfile(&ccf->pid, cycle->log) != NGX_OK) {
58 + if (ngx_create_pidfile(&ccf->pid, cycle->log) != NGX_OK) {
66 if (ngx_log_redirect_stderr(cycle) != NGX_OK) {

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