hw/riscv/riscv-iommu-hpm.c

27 /* For now we assume IOMMU HPM frequency to be 1GHz so 1-cycle is of 1-ns. */
35     const uint64_t cycle = riscv_iommu_reg_get64(  in riscv_iommu_hpmcycle_read()  local
42     trace_riscv_iommu_hpm_read(cycle, inhibit, ctr_prev, ctr_val);  in riscv_iommu_hpmcycle_read()
51                (cycle & RISCV_IOMMU_IOHPMCYCLES_OVF);  in riscv_iommu_hpmcycle_read()
55         (cycle & RISCV_IOMMU_IOHPMCYCLES_OVF);  in riscv_iommu_hpmcycle_read()
71          * Generate interrupt only if OF bit is clear. +1 to offset the cycle  in hpm_incr_ctr()
174 /* Timer callback for cycle counter overflow. */
221      * We are using INT64_MAX here instead to UINT64_MAX because cycle counter  in hpm_setup_timer()
240 /* Updates the internal cycle counter state when iocntinh:CY is changed. */
255          * Cycle counter is enabled. Just start the timer again and update  in riscv_iommu_process_iocntinh_cy()
263          * Cycle counter is disabled. Stop the timer and update the cycle  in riscv_iommu_process_iocntinh_cy()
368         /* +1 to offset CYCLE register OF bit. */  in riscv_iommu_process_hpmevt_write()