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/openbmc/linux/drivers/crypto/nx/
H A Dnx-common-powernv.c174 #define CSB_ERR(csb, msg, ...) \ argument
176 ##__VA_ARGS__, (csb)->flags, \
177 (csb)->cs, (csb)->cc, (csb)->ce, \
178 be32_to_cpu((csb)->count))
180 #define CSB_ERR_ADDR(csb, msg, ...) \ argument
181 CSB_ERR(csb, msg " at %lx", ##__VA_ARGS__, \
182 (unsigned long)be64_to_cpu((csb)->address))
185 struct coprocessor_status_block *csb) in wait_for_csb() argument
190 while (!(READ_ONCE(csb->flags) & CSB_V)) { in wait_for_csb()
197 /* hw has updated csb and output buffer */ in wait_for_csb()
[all …]
H A Dnx-common-pseries.c87 /* I assume we need to align the CSB? */
222 struct cop_status_block *csb) in nx842_validate_result() argument
224 /* The csb must be valid after returning from vio_h_cop_sync */ in nx842_validate_result()
225 if (!NX842_CSBCBP_VALID_CHK(csb->valid)) { in nx842_validate_result()
229 csb->valid, in nx842_validate_result()
230 csb->crb_seq_number, in nx842_validate_result()
231 csb->completion_code, in nx842_validate_result()
232 csb->completion_extension); in nx842_validate_result()
234 be32_to_cpu(csb->processed_byte_count), in nx842_validate_result()
235 (unsigned long)be64_to_cpu(csb->address)); in nx842_validate_result()
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/openbmc/linux/arch/powerpc/platforms/book3s/
H A Dvas-api.c138 * Update the CSB to indicate a translation error.
140 * User space will be polling on CSB after the request is issued.
141 * If NX can handle the request without any issues, it updates CSB.
143 * fault and update CSB with translation error.
145 * If we are unable to update the CSB means copy_to_user failed due to
151 struct coprocessor_status_block csb; in vas_update_csb() local
167 memset(&csb, 0, sizeof(csb)); in vas_update_csb()
168 csb.cc = CSB_CC_FAULT_ADDRESS; in vas_update_csb()
169 csb.ce = CSB_CE_TERMINATION; in vas_update_csb()
170 csb.cs = 0; in vas_update_csb()
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/openbmc/linux/Documentation/powerpc/
H A Dvas-api.rst217 co-processor Status Block (CSB) flags. NX updates status in CSB after each
218 request is processed. Refer NX-GZIP user's manual for the format of CSB and
221 In case if NX encounters translation error (called NX page fault) on CSB
225 updating CSB with the following data::
227 csb.flags = CSB_V;
228 csb.cc = CSB_CC_FAULT_ADDRESS;
229 csb.ce = CSB_CE_TERMINATION;
230 csb.address = fault_address;
236 If the OS can not update CSB due to invalid CSB address, sends SEGV signal
243 siginfo.si_addr = CSB address;
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/openbmc/linux/tools/testing/selftests/powerpc/nx-gzip/
H A Dgzip_vas.c152 while (getnn(cmdp->crb.csb, csb_v) == 0) { in nx_wait_for_csb()
180 /* hw has updated csb and output buffer */ in nx_wait_for_csb()
183 /* Check CSB flags. */ in nx_wait_for_csb()
184 if (getnn(cmdp->crb.csb, csb_v) == 0) { in nx_wait_for_csb()
185 fprintf(stderr, "CSB still not valid after %d polls.\n", in nx_wait_for_csb()
187 prt_err("CSB still not valid after %d polls, giving up.\n", in nx_wait_for_csb()
269 cc = getnn(cmdp->crb.csb, csb_cc); /* CC Table 6-8 */ in nxu_submit_job()
H A Dgzfht_test.c26 * csb: coprocessor status block (status)
92 memset((void *) &cmdp->crb.csb, 0, sizeof(cmdp->crb.csb)); in compress_fht_sample()
102 /* Figure 6-3 6-4; CSB location */ in compress_fht_sample()
105 (uint64_t) &cmdp->crb.csb & csb_address_mask); in compress_fht_sample()
284 (unsigned long long) cmdp->crb.csb.fsaddr)); in compress_file()
309 tpbc = get32(cmdp->crb.csb, tpbc); in compress_file()
H A Dgunz_test.c21 * csb: coprocessor status block (status)
250 memset((void *)&cmdp->crb.csb, 0, sizeof(cmdp->crb.csb)); in nx_submit_job()
256 csbaddr = ((uint64_t) &cmdp->crb.csb) & csb_address_mask; in nx_submit_job()
708 (void *)cmdp->crb.csb.fsaddr)); in decompress_file()
740 nx_ce = get_csb_ce_ms3b(cmdp->crb.csb); in decompress_file()
750 tpbc = get32(cmdp->crb.csb, tpbc); in decompress_file()
780 tpbc = get32(cmdp->crb.csb, tpbc); in decompress_file()
/openbmc/u-boot/Documentation/devicetree/bindings/board/
H A Dgdsys,board_gazerbeam.txt9 - csb: phandle to the board's coherent system bus (CSB) device node
22 csb = <&board_soc>;
/openbmc/u-boot/drivers/timer/
H A Dmpc83xx_timer.c93 struct udevice *csb; in interrupt_init() local
115 "csb", &csb); in interrupt_init()
117 debug("%s: Could not retrieve CSB device (error: %d)", in interrupt_init()
122 ret = clk_get_by_index(csb, 0, &clock); in interrupt_init()
/openbmc/linux/tools/testing/selftests/powerpc/nx-gzip/include/
H A Dnxu.h56 * csb: coprocessor status block (status)
113 /* 16B CSB size. Written to 0 by DMA when it writes the CPB */
129 /* Section 6.12.1 CSB NonZero error summary. FSA Failing storage
131 * to A field of CSB
314 /* byte[64:239] shift csb by 128 bytes out of the crb; csb was
315 * in crb earlier; JReilly says csb written with partial inject
320 volatile struct nx_csb_t csb; member
346 /* CSB */
530 /* CSB.CC Error codes */
636 struct nx_csb_t csb; member
H A Dcrb.h36 /* Chapter 6.5.7 Coprocessor-Status Block (CSB) */
110 * ADDRESS address of CSB
132 struct coprocessor_status_block csb; member
/openbmc/linux/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c418 * SYS -> CSB -> IPS) from the REF clock rate and the returned mul/div
457 calc_freq *= *ips_div; /* IPS -> CSB */ in mpc512x_clk_setup_ref_clock()
458 calc_freq *= 2; /* CSB -> SYS */ in mpc512x_clk_setup_ref_clock()
640 * CSB which is greater than IPS; the serial port setup may have in mpc512x_clk_setup_mclk()
734 /* now setup the REF -> SYS -> CSB -> IPS hierarchy */ in mpc512x_clk_setup_clock_tree()
737 clks[MPC512x_CLK_CSB] = mpc512x_clk_factor("csb", "sys", 1, 2); in mpc512x_clk_setup_clock_tree()
738 clks[MPC512x_CLK_IPS] = mpc512x_clk_divtable("ips", "csb", in mpc512x_clk_setup_clock_tree()
741 /* now setup anything below SYS and CSB and IPS */ in mpc512x_clk_setup_clock_tree()
756 clks[MPC512x_CLK_SDHC_x4] = mpc512x_clk_factor("sdhc-x4", "csb", 2, 1); in mpc512x_clk_setup_clock_tree()
766 clks[MPC512x_CLK_DIU_x4] = mpc512x_clk_factor("diu-x4", "csb", 4, 1); in mpc512x_clk_setup_clock_tree()
[all …]
/openbmc/u-boot/drivers/clk/
H A Dmpc83xx_clk.h35 * @core_csb_ratio: Core clock frequency to CSB clock frequency ratio
44 * Table with all valid Core CSB frequency ratio / VCO divider combinations as
92 * as a divider for the CSB clock to compute the
97 * as a multiplier for the CSB clock to compute the
323 * get_csb_clk() - Read the CSB (Coheren System Bus) clock speed
326 * Return: The CSB clock speed value as a 32-bit number.
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_execlists_submission.c154 #define GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE (0x1) /* lower csb dword */
155 #define GEN12_CTX_SWITCH_DETAIL(csb_dw) ((csb_dw) & 0xF) /* upper csb dword */
161 #define XEHP_CTX_STATUS_SWITCHED_TO_NEW_QUEUE BIT(1) /* upper csb dword */
838 * becomes a sentinel in parallel to CSB processing. in assert_pending_valid()
920 * that all ELSP are drained i.e. we have processed the CSB, in execlists_submit_ports()
1692 * Xe_HP csb shuffles things around compared to TGL:
1730 static bool xehp_csb_parse(const u64 csb) in xehp_csb_parse() argument
1732 return __gen12_csb_parse(XEHP_CSB_CTX_VALID(lower_32_bits(csb)), /* cxt to */ in xehp_csb_parse()
1733 XEHP_CSB_CTX_VALID(upper_32_bits(csb)), /* cxt away */ in xehp_csb_parse()
1734 upper_32_bits(csb) & XEHP_CTX_STATUS_SWITCHED_TO_NEW_QUEUE, in xehp_csb_parse()
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dicswx.h42 /* Chapter 6.5.7 Coprocessor-Status Block (CSB) */
131 * ADDRESS address of CSB
158 struct coprocessor_status_block csb; member
/openbmc/linux/drivers/iio/pressure/
H A Dms5611_i2c.c9 * 0x77 (CSB pin low)
10 * 0x76 (CSB pin high)
/openbmc/u-boot/include/configs/
H A DMPC837XEMDS.h33 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
82 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
83 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
84 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
/openbmc/u-boot/Documentation/devicetree/bindings/timer/
H A Dfsl,mpc83xx-timer.txt8 - clocks: must be a reference to the system's CSB (coherent system bus) clock,
/openbmc/u-boot/Documentation/devicetree/bindings/cpu/
H A Dfsl,mpc83xx.txt16 the CSB (Coherent System Bus) clock at index 1. Both are given by a suitable
/openbmc/linux/drivers/gpio/
H A Dgpio-stmpe.c24 enum { LSB, CSB, MSB }; enumerator
185 [REG_RE][CSB] = STMPE_IDX_GPRER_CSB, in stmpe_gpio_irq_sync_unlock()
188 [REG_FE][CSB] = STMPE_IDX_GPFER_CSB, in stmpe_gpio_irq_sync_unlock()
191 [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB, in stmpe_gpio_irq_sync_unlock()
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dexeclist.c158 /* Update the CSB and CSB write pointer in HWSP */ in emulate_csb_update()
170 gvt_dbg_el("vgpu%d: w pointer %u reg %x csb l %x csb h %x\n", in emulate_csb_update()
/openbmc/linux/drivers/ata/
H A Dpata_serverworks.c123 * serverworks_is_csb - Check for CSB or OSB
126 * Returns true if the device being checked is known to be a CSB
210 /* The OSB4 just requires the timing but the CSB series want the in serverworks_set_piomode()
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmpc5125twr.dts39 timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
40 bus-frequency = <198000000>; // 198 MHz csb bus
/openbmc/u-boot/drivers/cpu/
H A Dmpc83xx_cpu.c257 debug("%s: Failed to get CSB clock (err = %d)\n", in mpc83xx_cpu_get_desc()
265 "%s, MPC%s%s%s, Rev: %d.%d at %s MHz, CSB: %s MHz", in mpc83xx_cpu_get_desc()
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dspl_minimal.c40 /* Optimize transactions between CSB and other devices */ in cpu_init_f()

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