| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | ti,gpmc-child.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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| /openbmc/linux/include/linux/platform_data/ |
| H A D | gpmc-omap.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
58 u32 page_burst_access; /* Multiple access word delay */
59 u32 access; /* Start-cycle to first data valid delay */
78 u32 t_ceasu; /* address setup to CS valid */
94 u32 t_ce; /* access time from CS asertion */
96 u32 t_cez_r; /* read CS deassertion to high Z */
97 u32 t_cez_w; /* write CS deassertion to high Z */
105 u32 t_bacc; /* burst access valid clock to output delay */
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| /openbmc/linux/drivers/memory/ |
| H A D | omap-gpmc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
32 #include <linux/omap-gpmc.h>
36 #include <linux/platform_data/mtd-nand-omap2.h>
38 #define DEVICE_NAME "omap-gpmc"
206 /* Structure to save gpmc cs context */
257 /* Define chip-selects as reserved by default until probe completes */
277 void gpmc_cs_write_reg(int cs, int idx, u32 val) in gpmc_cs_write_reg() argument
281 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; in gpmc_cs_write_reg()
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| /openbmc/linux/include/linux/spi/ |
| H A D | spi.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later
33 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
39 * struct spi_statistics - statistics for spi transfers
40 * @syncp: seqcount to protect members in this struct for per-cpu update
41 * on 32-bit systems
43 * @messages: number of spi-messages handled
92 u64_stats_update_begin(&__lstats->syncp); \
93 u64_stats_add(&__lstats->field, count); \
94 u64_stats_update_end(&__lstats->syncp); \
103 u64_stats_update_begin(&__lstats->syncp); \
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| /openbmc/linux/net/ipv4/ |
| H A D | tcp_vegas.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * IEEE Journal on Selected Areas in Communication, 13(8):1465--1480,
10 * ftp://ftp.cs.arizona.edu/xkernel/Papers/jsac.ps
12 * See http://www.cs.arizona.edu/xkernel/ for their implementation.
17 * using fine-grained timers, NewReno, and FACK.
19 * only every-other RTT during slow start, we increase during
29 * o When the sender re-starts from idle, it waits until it has
55 /* There are several situations when we must "re-start" Vegas:
65 * stale info -- both the saved cwnd and congestion feedback are
77 vegas->doing_vegas_now = 1; in vegas_enable()
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| /openbmc/linux/drivers/spi/ |
| H A D | spi-mt7621.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // spi-mt7621.c -- MediaTek MT7621 SPI controller driver
6 // Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
7 // Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
9 // Some parts are based on spi-orion.c:
11 // Copyright (C) 2007-2008 Marvell Ltd.
14 #include <linux/delay.h>
23 #define DRIVER_NAME "spi-mt7621"
65 return spi_controller_get_devdata(spi->master); in spidev_to_mt7621_spi()
70 return ioread32(rs->base + reg); in mt7621_spi_read()
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| H A D | spi-imx.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
8 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
26 #include <linux/dma/imx-dma.h>
133 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
138 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
143 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi()
148 return d->devtype_data->devtype == IMX53_ECSPI; in is_imx53_ecspi()
154 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
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| H A D | spi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk/clk-conf.h>
10 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
35 #include <linux/spi/spi-mem.h>
51 spi_controller_put(spi->controller); in spidev_release()
52 kfree(spi->driver_override); in spidev_release()
53 free_percpu(spi->pcpu_statistics); in spidev_release()
63 len = acpi_device_modalias(dev, buf, PAGE_SIZE - 1); in modalias_show()
64 if (len != -ENODEV) in modalias_show()
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | omap_gpmc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
46 uint8_t cs; member
54 * omap_nand_hwcontrol - Set the address pointers corretly for the
62 int cs = info->cs; in omap_nand_hwcontrol() local
70 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; in omap_nand_hwcontrol()
73 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr; in omap_nand_hwcontrol()
76 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; in omap_nand_hwcontrol()
81 writeb(cmd, this->IO_ADDR_W); in omap_nand_hwcontrol()
89 return gpmc_cfg->status & (1 << (8 + info->ws)); in omap_dev_ready()
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| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | pl35x-nand-controller.c | 1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/delay.h>
31 #define PL35X_NANDC_DRIVER_NAME "pl35x-nand-controller"
119 unsigned int cs; member
126 * struct pl35x_nandc - NAND flash controller driver structure
133 * @assigned_cs: List of assigned CS
162 if (section >= chip->ecc.steps) in pl35x_ecc_ooblayout16_ecc()
163 return -ERANGE; in pl35x_ecc_ooblayout16_ecc()
165 oobregion->offset = (section * chip->ecc.bytes); in pl35x_ecc_ooblayout16_ecc()
166 oobregion->length = chip->ecc.bytes; in pl35x_ecc_ooblayout16_ecc()
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| H A D | marvell_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
33 * ECC) sections and potentially an extra one to deal with
39 * +-----------------------------------------
41 * +-----------------------------------------
43 * -------------------------------------------
45 * -------------------------------------------
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| H A D | arasan-nand-controller.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
114 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
124 * struct anfc_op - Defines how to execute an operation
150 * struct anand - Defines the NAND chip related information
153 * @rb: Ready-busy line
157 * @timings: NV-DDR specific timings to use
167 * @cs_idx: Array of chip-select for this device, values are indexes
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| /openbmc/linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_migrate.c | 1 // SPDX-License-Identifier: MIT
19 #define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
33 GEM_BUG_ON(engine->class != COPY_ENGINE_CLASS); in engine_supports_migration()
48 vm->insert_page(vm, 0, d->offset, in xehpsdv_toggle_pdes()
49 i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE), in xehpsdv_toggle_pdes()
51 GEM_BUG_ON(!pt->is_compact); in xehpsdv_toggle_pdes()
52 d->offset += SZ_2M; in xehpsdv_toggle_pdes()
68 vm->insert_page(vm, px_dma(pt), d->offset, in xehpsdv_insert_pte()
69 i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE), in xehpsdv_insert_pte()
71 d->offset += SZ_64K; in xehpsdv_insert_pte()
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| H A D | intel_ring_submission.c | 1 // SPDX-License-Identifier: MIT
3 * Copyright © 2008-2021 Intel Corporation
31 * set-context and then emitting the batch.
41 if (engine->class == RENDER_CLASS) { in set_hwstam()
42 if (GRAPHICS_VER(engine->i915) >= 6) in set_hwstam()
56 if (GRAPHICS_VER(engine->i915) >= 4) in set_hws_pga()
59 intel_uncore_write(engine->uncore, HWS_PGA, addr); in set_hws_pga()
64 struct drm_i915_gem_object *obj = engine->status_page.vma->obj; in status_page()
67 return sg_page(obj->mm.pages->sgl); in status_page()
84 if (GRAPHICS_VER(engine->i915) == 7) { in set_hwsp()
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| H A D | intel_engine_cs.c | 1 // SPDX-License-Identifier: MIT
40 * on HSW) - so the final size, including the extra state required for the
260 * intel_engine_context_size() - return the size of the context for an engine
275 struct intel_uncore *uncore = gt->uncore; in intel_engine_context_size()
284 switch (GRAPHICS_VER(gt->i915)) { in intel_engine_context_size()
286 MISSING_CASE(GRAPHICS_VER(gt->i915)); in intel_engine_context_size()
296 if (IS_HASWELL(gt->i915)) in intel_engine_context_size()
319 drm_dbg(>->i915->drm, in intel_engine_context_size()
321 GRAPHICS_VER(gt->i915), cxt_size * 64, in intel_engine_context_size()
322 cxt_size - 1); in intel_engine_context_size()
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| H A D | intel_execlists_submission.c | 1 // SPDX-License-Identifier: MIT
19 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
20 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
26 * rings, the engine cs shifts to a new "ring buffer" with every context
37 * - One global default context.
38 * - One local default context for each opened fd.
39 * - One local extra context for each context create ioctl call.
41 * Now that ringbuffers belong per-context (and not per-engine, like before)
45 * - One ringbuffer per-engine inside each context.
46 * - One backing object per-engine inside each context.
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| /openbmc/linux/include/linux/mtd/ |
| H A D | rawnand.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
75 #define NAND_CMD_NONE -1
84 #define NAND_DATA_IFACE_CHECK_ONLY -1
98 * ecc.correct() returns -EBADMSG.
124 * Chip requires ready check on read (for auto-incremented sequential read).
142 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
174 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
175 * on the default ->cmdfunc() implementation, you may want to let the core
176 * handle the tCCS delay which is required when a column change (RNDIN or
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| /openbmc/u-boot/board/freescale/m5373evb/ |
| H A D | README | 4 TsiChung Liew(Tsi-Chung.Liew@freescale.com)
12 - board/freescale/m5373evb/m5373evb.c Dram setup
13 - board/freescale/m5373evb/mii.c Mii access
14 - board/freescale/m5373evb/Makefile Makefile
15 - board/freescale/m5373evb/config.mk config make
16 - board/freescale/m5373evb/u-boot.lds Linker description
18 - arch/m68k/cpu/mcf532x/cpu.c cpu specific code
19 - arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
20 - arch/m68k/cpu/mcf532x/interrupts.c cpu specific interrupt support
21 - arch/m68k/cpu/mcf532x/speed.c system, pci, flexbus, and cpu clock
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| /openbmc/linux/drivers/infiniband/hw/qib/ |
| H A D | qib_iba6120.c | 2 * Copyright (c) 2013 - 2017 Intel Corporation. All rights reserved.
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
42 #include <linux/delay.h>
54 * This file contains all the chip-specific register information and
55 * access functions for the Intel Intel_IB PCI-Express chip.
59 /* KREG_IDX uses machine-generated #defines */
62 /* Use defines to tie machine-generated names to lower-case names */
115 #define CREG_IDX(regname) ((QIB_6120_##regname##_OFFS - \
237 * DDR when faking DDR negotiations with non-IBTA switches.
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| /openbmc/linux/include/linux/iio/imu/ |
| H A D | adis.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
26 * struct adis_timeouts - ADIS chip variant timeouts
27 * @reset_ms - Wait time after rst pin goes inactive
28 * @sw_reset_ms - Wait time after sw reset command
29 * @self_test_ms - Wait time after self test command
38 * struct adis_data - ADIS chip variant specific data
39 * @read_delay: SPI delay for read operations in us
40 * @write_delay: SPI delay for write operations in us
41 * @cs_change_delay: SPI delay between CS changes in us
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| /openbmc/linux/drivers/iio/adc/ |
| H A D | ad7923.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright 2012 CS Systemes d'Information
17 #include <linux/delay.h>
47 #define EXTRACT(val, dec, bits) (((val) >> (dec)) & ((1 << (bits)) - 1))
64 * Length = 8 channels + 4 extra for 8 byte timestamp
97 .shift = 12 - (bits), \
172 for_each_set_bit(i, active_scan_mask, indio_dev->num_channels - 1) { in ad7923_update_scan_mode()
175 st->settings; in ad7923_update_scan_mode()
177 st->tx_buf[len++] = cpu_to_be16(cmd); in ad7923_update_scan_mode()
180 st->ring_xfer[0].tx_buf = &st->tx_buf[0]; in ad7923_update_scan_mode()
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| /openbmc/linux/Documentation/spi/ |
| H A D | spi-summary.rst | 5 02-Feb-2012
8 ------------
17 clocking modes through which data is exchanged; mode-0 and mode-3 are most
32 - SPI may be used for request/response style device protocols, as with
35 - It may also be used to stream data in either direction (half duplex),
38 - Some devices may use eight bit words. Others may use different word
39 lengths, such as streams of 12-bit or 20-bit digital samples.
41 - Words are usually sent with their most significant bit (MSB) first,
44 - Sometimes SPI is used to daisy-chain devices, like shift registers.
51 SPI is only one of the names used by such four-wire protocols, and
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| /openbmc/linux/drivers/net/wireless/legacy/ |
| H A D | wl3501_cs.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 * 5. ISA card driver - wl24.c
15 * 6. Linux PCMCIA skeleton driver - skeleton.c
16 * 7. Linux PCMCIA 3c589 network driver - 3c589_cs.c
18 * Tested with WL2400 firmware 1.2, Linux 2.0.30, and pcmcia-cs-2.9.12
19 * 1. Performance: about 165 Kbytes/sec in TCP/IP with Ad-Hoc mode.
27 * Tested with Planet AP in 2.5.73-bk, 216 Kbytes/s in Infrastructure mode
31 #include <linux/delay.h>
63 /* For rough constant delay */
136 * iw_valid_channel - validate channel in regulatory domain
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| /openbmc/linux/arch/arm/mach-sa1100/ |
| H A D | generic.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-sa1100/generic.c
14 #include <linux/delay.h>
15 #include <linux/dma-mapping.h>
23 #include <linux/irqchip/irq-sa11x0.h>
75 * Default power-off for SA1100
81 /* disable internal oscillator, float CS lines */ in sa1100_power_off()
83 /* enable wake-up on GPIO0 (Assabet...) */ in sa1100_power_off()
102 /* Use on-chip reset capability */ in sa11x0_restart()
110 dev->dev.platform_data = data; in sa11x0_register_device()
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| /openbmc/u-boot/drivers/ddr/altera/ |
| H A D | sequencer.c | 1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright Altera Corporation (C) 2012-2015
44 * However, to support simulation-time selection of fast simulation mode, where
47 * check, which is based on the rtl-supplied value, or we dynamically compute
48 * the value to use based on the dynamically-chosen calibration mode
64 * non-skip and skip values
66 * The mask is set to include all bits when not-skipping, but is
70 static u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */
85 if (gbl->error_stage == CAL_STAGE_NIL) { in set_failing_group_stage()
86 gbl->error_substage = substage; in set_failing_group_stage()
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