Searched +full:cpu +full:- +full:capacity (Results 1 – 25 of 271) sorted by relevance
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2 Capacity Aware Scheduling5 1. CPU Capacity9 ----------------13 different performance characteristics - on such platforms, not all CPUs can be16 CPU capacity is a measure of the performance a CPU can reach, normalized against17 the most performant CPU in the system. Heterogeneous systems are also called18 asymmetric CPU capacity systems, as they contain CPUs of different capacities.20 Disparity in maximum attainable performance (IOW in maximum CPU capacity) stems23 - not all CPUs may have the same microarchitecture (µarch).24 - with Dynamic Voltage and Frequency Scaling (DVFS), not all CPUs may be[all …]
6 ---------------10 Energy Model (EM) of the CPUs to select an energy efficient CPU for each task,17 /!\ EAS does not support platforms with symmetric CPU topologies /!\19 EAS operates only on heterogeneous CPU topologies (such as Arm big.LITTLE)25 please refer to its documentation (see Documentation/power/energy-model.rst).29 -----------------------------32 - energy = [joule] (resource like a battery on powered devices)33 - power = energy/time = [joule/second] = [watt]39 --------------------45 -----------[all …]
7 All this assumes a linear relation between frequency and work capacity,15 individual tasks to task-group slices to CPU runqueues. As the basis for this31 Note that blocked tasks still contribute to the aggregates (task-group slices32 and CPU runqueues), which reflects their expected contribution when they36 reflects the time an entity spends on the CPU, while 'runnable' reflects the38 two metrics are the same, but once there is contention for the CPU 'running'39 will decrease to reflect the fraction of time each task spends on the CPU45 Frequency / CPU Invariance48 Because consuming the CPU for 50% at 1GHz is not the same as consuming the CPU49 for 50% at 2GHz, nor is running 50% on a LITTLE CPU the same as running 50% on[all …]
2 CPU capacity bindings6 1 - Introduction15 2 - CPU capacity definition18 CPU capacity is a number that provides the scheduler information about CPUs19 heterogeneity. Such heterogeneity can come from micro-architectural differences23 capture a first-order approximation of the relative performance of CPUs.25 CPU capacities are obtained by running a suitable benchmark. This binding makes27 final capacity should, however, be:29 * A "single-threaded" or CPU affine benchmark30 * Divided by the running frequency of the CPU executing the benchmark[all …]
15 #include <linux/cpu.h>29 #include <asm/cpu.h>34 * cpu capacity scale management38 * cpu capacity table39 * This per cpu data structure describes the relative capacity of each core.40 * On a heteregenous system, cores don't have the same computation capacity42 * can take this difference into account during load balance. A per cpu43 * structure is preferred because each CPU updates its own cpu_capacity field61 * is used to compute the capacity of a CPU.66 {"arm,cortex-a15", 3891},[all …]
1 .. SPDX-License-Identifier: GPL-2.02 .. include:: ../disclaimer-zh_CN.rst4 :Original: Documentation/scheduler/sched-capacity.rst22 --------27 我们引入CPU算力（capacity）的概念来测量每个CPU能达到的性能，它的值相对系统中性能最强的CPU32 - 不是所有CPU的微架构都相同。33 - 在动态电压频率升降（Dynamic Voltage and Frequency Scaling，DVFS）框架中，不是所有的CPU都34 能达到一样高的操作性能值（Operating Performance Points，OPP。译注，也就是“频率-电压”对）。42 capacity(cpu) = work_per_hz(cpu) * max_freq(cpu)45 --------------[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Samsung Exynos5422 SoC cpu device tree source8 * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.10 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos542215 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting16 * from the LITTLE: Cortex-A7.21 #address-cells = <1>;22 #size-cells = <0>;24 cpu-map {[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Samsung Exynos5420 SoC cpu device tree source9 * boards: CPU[0123] being the A15.11 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos542216 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting17 * from the LITTLE: Cortex-A7.22 #address-cells = <1>;23 #size-cells = <0>;25 cpu-map {[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Arch specific cpu topology information11 #include <linux/cpu.h>63 int cpu; in topology_set_scale_freq_source() local74 for_each_cpu(cpu, cpus) { in topology_set_scale_freq_source()75 sfd = rcu_dereference(*per_cpu_ptr(&sft_data, cpu)); in topology_set_scale_freq_source()78 if (!sfd || sfd->source != SCALE_FREQ_SOURCE_ARCH) { in topology_set_scale_freq_source()79 rcu_assign_pointer(per_cpu(sft_data, cpu), data); in topology_set_scale_freq_source()80 cpumask_set_cpu(cpu, &scale_freq_counters_mask); in topology_set_scale_freq_source()94 int cpu; in topology_clear_scale_freq_source() local[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)7 #include "meson-gxl.dtsi"10 compatible = "amlogic,meson-gxm";13 cpu-map {16 cpu = <&cpu0>;19 cpu = <&cpu1>;22 cpu = <&cpu2>;25 cpu = <&cpu3>;31 cpu = <&cpu4>;34 cpu = <&cpu5>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)7 #include "meson-g12.dtsi"13 #address-cells = <0x2>;14 #size-cells = <0x0>;16 cpu-map {19 cpu = <&cpu0>;23 cpu = <&cpu1>;29 cpu = <&cpu100>;33 cpu = <&cpu101>;37 cpu = <&cpu102>;[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT10 #include <dt-bindings/gpio/gpio.h>11 #include <dt-bindings/interrupt-controller/apple-aic.h>12 #include <dt-bindings/interrupt-controller/irq.h>13 #include <dt-bindings/pinctrl/apple.h>15 #include "multi-die-cpp.h"17 #include "t600x-common.dtsi"20 compatible = "apple,t6002", "apple,arm-platform";22 #address-cells = <2>;23 #size-cells = <2>;[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT11 #address-cells = <2>;12 #size-cells = <2>;15 #address-cells = <2>;16 #size-cells = <0>;18 cpu-map {21 cpu = <&cpu_e00>;24 cpu = <&cpu_e01>;30 cpu = <&cpu_p00>;33 cpu = <&cpu_p01>;[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */3 * sched-domains (multiprocessor balancing) flag declarations.29 * certain level (e.g. domain starts spanning CPUs outside of the base CPU's78 * Consider waking task on waking CPU.85 * Domain members have different CPU capacities89 * NEEDS_GROUPS: Per-CPU capacity is asymmetric between groups.94 * Domain members have different CPU capacities spanning all unique CPU95 * capacity values.98 * all available CPU capacities are visible99 * NEEDS_GROUPS: Per-CPU capacity is asymmetric between groups.[all …]
9 /dts-v1/;11 #include <dt-bindings/interrupt-controller/arm-gic.h>12 #include <dt-bindings/arm/coresight-cti-dt.h>13 #include "juno-base.dtsi"14 #include "juno-cs-r1r2.dtsi"18 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";19 interrupt-parent = <&gic>;20 #address-cells = <2>;21 #size-cells = <2>;28 stdout-path = "serial0:115200n8";[all …]
4 * Copyright (c) 2013-2014 ARM Ltd.9 /dts-v1/;11 #include <dt-bindings/interrupt-controller/arm-gic.h>12 #include <dt-bindings/arm/coresight-cti-dt.h>13 #include "juno-base.dtsi"18 interrupt-parent = <&gic>;19 #address-cells = <2>;20 #size-cells = <2>;27 stdout-path = "serial0:115200n8";31 compatible = "arm,psci-0.2";[all …]
9 /dts-v1/;11 #include <dt-bindings/interrupt-controller/arm-gic.h>12 #include <dt-bindings/arm/coresight-cti-dt.h>13 #include "juno-base.dtsi"14 #include "juno-cs-r1r2.dtsi"18 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";19 interrupt-parent = <&gic>;20 #address-cells = <2>;21 #size-cells = <2>;28 stdout-path = "serial0:115200n8";[all …]
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: RISC-V CPUs10 - Paul Walmsley <paul.walmsley@sifive.com>11 - Palmer Dabbelt <palmer@sifive.com>12 - Conor Dooley <conor@kernel.org>15 This document uses some terminology common to the RISC-V community19 mandated by the RISC-V ISA: a PC and some registers. This27 - $ref: /schemas/cpu.yaml#[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Ilia Lin <ilia.lin@kernel.org>13 - $ref: opp-v2-base.yaml#17 the CPU frequencies subset and voltage value of each OPP varies based on22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide25 operating-points-v2 table when it is parsed by the OPP framework.29 const: operating-points-v2-kryo-cpu[all …]
1 // SPDX-License-Identifier: GPL-2.043 #include <linux/memory-tiers.h>61 * The initial- and re-scaling of tunables is configurable65 * SCHED_TUNABLESCALING_NONE - unscaled, always *166 * SCHED_TUNABLESCALING_LOG - scaled logarithmical, *1+ilog(ncpus)67 * SCHED_TUNABLESCALING_LINEAR - scaled linear, *ncpus74 * Minimal preemption granularity for CPU-bound tasks:104 * For asym packing, by default the lower numbered CPU has higher priority.106 int __weak arch_asym_cpu_priority(int cpu) in arch_asym_cpu_priority() argument108 return -cpu; in arch_asym_cpu_priority()[all …]
1 // SPDX-License-Identifier: GPL-2.035 static int sched_domain_debug_one(struct sched_domain *sd, int cpu, int level, in sched_domain_debug_one() argument38 struct sched_group *group = sd->groups; in sched_domain_debug_one()39 unsigned long flags = sd->flags; in sched_domain_debug_one()44 printk(KERN_DEBUG "%*s domain-%d: ", level, "", level); in sched_domain_debug_one()46 cpumask_pr_args(sched_domain_span(sd)), sd->name); in sched_domain_debug_one()48 if (!cpumask_test_cpu(cpu, sched_domain_span(sd))) { in sched_domain_debug_one()49 printk(KERN_ERR "ERROR: domain->span does not contain CPU%d\n", cpu); in sched_domain_debug_one()51 if (group && !cpumask_test_cpu(cpu, sched_group_span(group))) { in sched_domain_debug_one()52 printk(KERN_ERR "ERROR: domain->groups does not contain CPU%d\n", cpu); in sched_domain_debug_one()[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */14 * struct em_perf_state - Performance state of a performance domain16 * @power: The power consumed at this level (by 1 CPU or by a registered40 * struct em_perf_domain - Performance domain49 * In case of CPU device, a "performance domain" represents a group of CPUs51 * must have the same micro-architecture. Performance domains often have52 * a 1-to-1 mapping with CPUFreq policies. In case of other devices the @cpus65 * EM_PERF_DOMAIN_MICROWATTS: The power values are in micro-Watts or some78 #define em_span_cpus(em) (to_cpumask((em)->cpus))79 #define em_is_artificial(em) ((em)->flags & EM_PERF_DOMAIN_ARTIFICIAL)[all …]
1 .. SPDX-License-Identifier: GPL-2.07 CPU Performance Scaling15 The Concept of CPU Performance Scaling20 Operating Performance Points or P-states (in ACPI terminology). As a rule,22 can be retired by the CPU over a unit of time, but also the higher the clock24 time (or the more power is drawn) by the CPU in the given P-state. Therefore25 there is a natural tradeoff between the CPU capacity (the number of instructions26 that can be executed over a unit of time) and the power drawn by the CPU.29 as possible and then there is no reason to use any P-states different from the30 highest one (i.e. the highest-performance frequency/voltage configuration[all …]
6 // clang-format off19 CPU, enumerator74 Capacity, enumerator93 {PhysicalContext::CPU, "CPU"},148 {LogicalContext::Capacity, "Capacity"},157 // clang-format on
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */41 * Sporadic Time-Constrained Task Attributes44 * A subset of sched_attr attributes allows to describe a so-called45 * sporadic time-constrained task.48 * - the activation period or minimum instance inter-arrival time;49 * - the maximum (or average, depending on the actual scheduling51 * - the deadline (relative to the actual activation time) of each54 * some specific computation --which is typically called an instance--86 * represents the percentage of CPU time used by a task when running at the87 * maximum frequency on the highest capacity CPU of the system. For example, a[all …]