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/openbmc/linux/tools/testing/selftests/cpu-hotplug/
H A Dcpu-on-off-test.sh2 # SPDX-License-Identifier: GPL-2.0
5 # Kselftest framework requirement - SKIP code is 4.
14 echo $msg must be run as root >&2
18 taskset -p 01 $$
20 SYSFS=`mount -t sysfs | head -1 | awk '{ print $3 }'`
22 if [ ! -d "$SYSFS" ]; then
23 echo $msg sysfs is not mounted >&2
27 if ! ls $SYSFS/devices/system/cpu/cpu* > /dev/null 2>&1; then
28 echo $msg cpu hotplug is not supported >&2
32 echo "CPU online/offline summary:"
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/openbmc/qemu/target/arm/tcg/
H A Dcpu32.c2 * QEMU ARM TCG-only CPUs.
8 * SPDX-License-Identifier: GPL-2.0-or-later
12 #include "cpu.h"
13 #include "hw/core/tcg-cpu-ops.h"
22 /* Share AArch32 -cpu max features with AArch64. */
23 void aa32_max_features(ARMCPU *cpu) in aa32_max_features() argument
28 t = cpu->isar.id_isar5; in aa32_max_features()
29 t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ in aa32_max_features()
35 cpu->isar.id_isar5 = t; in aa32_max_features()
37 t = cpu->isar.id_isar6; in aa32_max_features()
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H A Dcpu64.c8 * as published by the Free Software Foundation; either version 2
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
23 #include "cpu.h"
26 #include "hw/qdev-properties.h"
29 #include "cpu-features.h"
34 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a35_initfn() local
36 cpu->dtb_compatible = "arm,cortex-a35"; in aarch64_a35_initfn()
37 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a35_initfn()
38 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a35_initfn()
39 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a35_initfn()
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/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a …
10 "Unit": "CPU-M-CF",
14 …s been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Leve…
17 "Unit": "CPU-M-CF",
21 …ress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progr…
24 "Unit": "CPU-M-CF",
28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
31 "Unit": "CPU-M-CF",
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/openbmc/linux/Documentation/translations/zh_CN/mm/
H A Dmmu_notifier.rst28 - 上页表锁
29 - 清除页表项并通知 ([pmd/pte]p_huge_clear_flush_notify())
30 - 设置页表项以指向新页
37 两个地址addrA和addrB，这样|addrA - addrB| >= PAGE_SIZE，我们假设它们是COW的
42 [Time N] --------------------------------------------------------------------
43 CPU-thread-0 {尝试写到addrA}
44 CPU-thread-1 {尝试写到addrB}
45 CPU-thread-2 {}
46 CPU-thread-3 {}
47 DEV-thread-0 {读取addrA并填充设备TLB}
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/openbmc/qemu/docs/specs/
H A Dacpi_cpu_hotplug.rst1 QEMU<->ACPI BIOS CPU hotplug interface
4 QEMU supports CPU hotplug via ACPI. This document
7 ACPI BIOS GPE.2 handler is dedicated for notifying OS about CPU hot-add
8 and hot-remove events.
11 Legacy ACPI CPU hotplug interface registers
12 -------------------------------------------
14 CPU present bitmap for:
16 - ICH9-LPC (IO port 0x0cd8-0xcf7, 1-byte access)
17 - PIIX-PM (IO port 0xaf00-0xaf1f, 1-byte access)
18 - One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-only.
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/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip05.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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/openbmc/linux/Documentation/mm/
H A Dmmu_notifier.rst8 For secondary TLB (non CPU TLB) like IOMMU TLB or device TLB (when device use
9 thing like ATS/PASID to get the IOMMU to walk the CPU page table to access a
10 process virtual address space). There is only 2 cases when you need to notify
23 - take page table lock
24 - clear page table entry and notify ([pmd/pte]p_huge_clear_flush_notify())
25 - set page table entry to point to new page
33 Two address addrA and addrB such that \|addrA - addrB\| >= PAGE_SIZE we assume
38 [Time N] --------------------------------------------------------------------
39 CPU-thread-0 {try to write to addrA}
40 CPU-thread-1 {try to write to addrB}
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/openbmc/qemu/target/arm/hvf/
H A Dhvf.c7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
13 #include "qemu/error-report.h"
24 #include "exec/address-spaces.h"
27 #include "qemu/main-loop.h"
29 #include "arm-powerctl.h"
30 #include "target/arm/cpu.h"
183 #define SYSREG_OSLAR_EL1 SYSREG(2, 0, 1, 0, 4)
184 #define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4)
185 #define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4)
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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls2080a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
15 &cpu {
16 cpu0: cpu@0 {
17 device_type = "cpu";
18 compatible = "arm,cortex-a57";
21 cpu-idle-states = <&CPU_PW20>;
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H A Dfsl-ls2088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2088A family SoC.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
15 &cpu {
16 cpu0: cpu@0 {
17 device_type = "cpu";
18 compatible = "arm,cortex-a72";
21 cpu-idle-states = <&CPU_PW20>;
22 next-level-cache = <&cluster0_l2>;
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/openbmc/qemu/docs/system/s390x/
H A Dcpu-topology.rst1 .. _cpu-topology-s390x:
3 CPU topology on s390x
6 Since QEMU 8.2, CPU topology on s390x provides up to 3 levels of
8 tree-shaped hierarchy.
10 The socket container has one or more CPU entries.
11 Each of these CPU entries consists of a bitmap and three CPU attributes:
13 - CPU type
14 - entitlement
15 - dedication
17 Each bit set in the bitmap correspond to a core-id of a vCPU with matching
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/openbmc/qemu/target/arm/
H A Dmachine.c2 #include "cpu.h"
3 #include "qemu/error-report.h"
8 #include "cpu-features.h"
9 #include "migration/cpu.h"
14 ARMCPU *cpu = opaque; in vfp_needed() local
16 return (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) in vfp_needed()
17 ? cpu_isar_feature(aa64_fp_simd, cpu) in vfp_needed()
18 : cpu_isar_feature(aa32_vfp_simd, cpu)); in vfp_needed()
27 * cpu/vfp/fpcr_fpsr subsection, and we will send a 0 for the old in vfp_fpcr_fpsr_needed()
28 * FPSCR field in cpu/vfp. in vfp_fpcr_fpsr_needed()
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H A Dkvm.c4 * Copyright Christoffer Dall 2009-2010
5 * Copyright Mian-M. Hamayun 2013, Virtual Open Systems
8 * This work is licensed under the terms of the GNU GPL, version 2 or later.
9 * See the COPYING file in the top-level directory.
19 #include "qemu/error-report.h"
20 #include "qemu/main-loop.h"
28 #include "cpu.h"
33 #include "exec/address-spaces.h"
54 * ARMHostCPUFeatures: information about the host CPU (identified
68 * @cpu: ARMCPU
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/openbmc/linux/tools/testing/selftests/net/forwarding/
H A Dtsn_lib.sh2 # SPDX-License-Identifier: GPL-2.0
3 # Copyright 2021-2022 NXP
13 # https://github.com/vladimiroltean/tsn-scripts
14 # WARNING: isochron versions pre-1.0 are unstable,
28 if ! [ -z "${uds_address}" ]; then
29 extra_args="${extra_args} -z ${uds_address}"
34 chrt -f 10 phc2sys -m \
35 -a -rr \
36 --step_threshold 0.00002 \
37 --first_step_threshold 0.00002 \
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/openbmc/qemu/tests/functional/
H A Dtest_s390x_topology.py10 # This work is licensed under the terms of the GNU GPL, version 2 or
11 # later. See the COPYING file in the top-level directory.
25 S390x CPU topology consists of 4 topology layers, from bottom to top,
26 the cores, sockets, books and drawers and 2 modifiers attributes,
28 See: docs/system/s390x/cpu-topology.rst.
30 S390x CPU topology is setup in different ways:
31 - implicitly from the '-smp' argument by completing each topology
34 - explicitly from the '-device' argument on the QEMU command line
35 - explicitly by hotplug of a new CPU using QMP or HMP
36 - it is modified by using QMP 'set-cpu-topology'
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/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5422 SoC cpu device tree source
8 * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
10 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu-map {
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H A Dexynos5420-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5420 SoC cpu device tree source
9 * boards: CPU[0123] being the A15.
11 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17 * from the LITTLE: Cortex-A7.
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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/openbmc/qemu/target/openrisc/
H A Dcpu.c2 * QEMU OpenRISC CPU
22 #include "qemu/qemu-print.h"
23 #include "cpu.h"
24 #include "exec/exec-all.h"
25 #include "fpu/softfloat-helpers.h"
30 OpenRISCCPU *cpu = OPENRISC_CPU(cs); in openrisc_cpu_set_pc() local
32 cpu->env.pc = value; in openrisc_cpu_set_pc()
33 cpu->env.dflag = 0; in openrisc_cpu_set_pc()
38 OpenRISCCPU *cpu = OPENRISC_CPU(cs); in openrisc_cpu_get_pc() local
40 return cpu->env.pc; in openrisc_cpu_get_pc()
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/openbmc/linux/Documentation/core-api/
H A Dworkqueue.rst32 worker thread per CPU and a single threaded (ST) wq had one worker
33 thread system-wide. A single MT wq needed to keep around the same
35 wq users over the years and with the number of CPU cores continuously
42 worker pool. An MT wq could provide only one execution context per CPU
60 * Use per-CPU unified worker pools shared by all wq to provide
83 called worker-pools.
85 The cmwq design differentiates between the user-facing workqueues that
87 which manages worker-pools and processes the queued work items.
89 There are two worker-pools, one for normal work items and the other
90 for high priority ones, for each possible CPU and some extra
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/openbmc/linux/Documentation/admin-guide/
H A Dkernel-per-CPU-kthreads.rst2 Reducing OS jitter due to per-cpu kthreads
5 This document lists per-CPU kthreads in the Linux kernel and presents
6 options to control their OS jitter. Note that non-per-CPU kthreads are
7 not listed here. To reduce OS jitter from non-per-CPU kthreads, bind
8 them to a "housekeeping" CPU dedicated to such work.
13 - Documentation/core-api/irq/irq-affinity.rst: Binding interrupts to sets of CPUs.
15 - Documentation/admin-guide/cgroup-v1: Using cgroups to bind tasks to sets of CPUs.
17 - man taskset: Using the taskset command to bind tasks to sets
20 - man sched_setaffinity: Using the sched_setaffinity() system
23 - /sys/devices/system/cpu/cpuN/online: Control CPU N's hotplug state,
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/openbmc/linux/arch/arm64/boot/dts/cavium/
H A Dthunder-88xx.dtsi2 * Cavium Thunder DTS file - Thunder SoC description
6 * This file is dual-licensed: you can use it either under the terms
13 * published by the Free Software Foundation; either version 2 of the
24 * MA 02110-1301 USA
51 compatible = "cavium,thunder-88xx";
52 interrupt-parent = <&gic0>;
53 #address-cells = <2>;
54 #size-cells = <2>;
57 compatible = "arm,psci-0.2";
62 #address-cells = <2>;
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/openbmc/linux/Documentation/translations/zh_TW/arch/arm64/
H A Dbooting.txt1 SPDX-License-Identifier: GPL-2.0
15 ---------------------------------------------------------------------
30 ---------------------------------------------------------------------
40 AArch64 異常模型由多個異常級（EL0 - EL3）組成，對於 EL0 和 EL1 異常級
45 這個術語來定義在將控制權交給 Linux 內核前 CPU 上執行的所有軟體。
52 2、設置設備樹數據
58 -----------------
68 2、設置設備樹數據
69 ---------------
73 設備樹數據塊（dtb）必須 8 字節對齊，且大小不能超過 2MB。由於設備樹
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/openbmc/linux/Documentation/translations/zh_CN/arch/arm64/
H A Dbooting.txt12 ---------------------------------------------------------------------
26 ---------------------------------------------------------------------
36 AArch64 异常模型由多个异常级（EL0 - EL3）组成，对于 EL0 和 EL1 异常级
41 这个术语来定义在将控制权交给 Linux 内核前 CPU 上执行的所有软件。
48 2、设置设备树数据
54 -----------------
64 2、设置设备树数据
65 ---------------
69 设备树数据块（dtb）必须 8 字节对齐，且大小不能超过 2MB。由于设备树
70 数据块将在使能缓存的情况下以 2MB 粒度被映射，故其不能被置于必须以特定
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/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Damlogic-t7.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <0x2>;
15 #size-cells = <0x0>;
17 cpu-map {
20 cpu = <&cpu100>;
23 cpu = <&cpu101>;
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