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/openbmc/qemu/docs/system/arm/
H A Dxlnx-zynq.rst1 Xilinx Zynq board (``xilinx-zynq-a9``)
4 integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based
8 https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technical-Reference-Manual
10 QEMU xilinx-zynq-a9 board supports following devices:
11 - A9 MPCORE
12 - cortex-a9
13 - GIC v1
14 - Generic timer
15 - wdt
16 - OCM 256KB
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H A Dnuvoton.rst1 Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta-gbs-bmc``, ``quanta-gsj`…
4 The `Nuvoton iBMC`_ chips are a family of Arm-based SoCs that are
7 NPCM8XX series. NPCM7XX series feature one or two Arm Cortex-A9 CPU cores,
8 while NPCM8XX feature 4 Arm Cortex-A35 CPU cores. Both series contain a
12 .. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/
14 The NPCM750 SoC has two Cortex-A9 cores and is targeted for the Enterprise
17 - ``npcm750-evb`` Nuvoton NPCM750 Evaluation board
19 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
22 - ``quanta-gbs-bmc`` Quanta GBS server BMC
23 - ``quanta-gsj`` Quanta GSJ server BMC
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H A Drealview.rst1 Arm Realview boards (``realview-eb``, ``realview-eb-mpcore``, ``realview-pb-a8``, ``realview-pbx-a9…
5 the EB, PB-A8 and PBX-A9. Due to interactions with the bootloader, only
8 Kernels for the PB-A8 board should have CONFIG_REALVIEW_HIGH_PHYS_OFFSET
9 enabled in the kernel, and expect 512M RAM. Kernels for The PBX-A9 board
15 - ARM926E, ARM1136, ARM11MPCore, Cortex-A8 or Cortex-A9 MPCore CPU
17 - Arm AMBA Generic/Distributed Interrupt Controller
19 - Four PL011 UARTs
21 - SMC 91c111 or SMSC LAN9118 Ethernet adapter
23 - PL110 LCD controller
25 - PL050 KMI with PS/2 keyboard and mouse
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H A Dhighbank.rst4 ``highbank`` is a model of the Calxeda Highbank (ECX-1000) system,
5 which has four Cortex-A9 cores.
7 ``midway`` is a model of the Calxeda Midway (ECX-2000) system,
8 which has four Cortex-A15 cores.
12 - L2x0 cache controller
13 - SP804 dual timer
14 - PL011 UART
15 - PL061 GPIOs
16 - PL031 RTC
17 - PL022 synchronous serial port controller
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H A Dexynos.rst4 These are machines which use the Samsung Exynos4210 SoC, which has Cortex-A9 CPUs.
H A Dvexpress.rst1 Arm Versatile Express boards (``vexpress-a9``, ``vexpress-a15``)
7 - ``vexpress-a9`` models the combination of the Versatile Express
9 - ``vexpress-a15`` models the combination of the Versatile Express
17 - PL041 audio
18 - PL181 SD controller
19 - PL050 keyboard and mouse
20 - PL011 UARTs
21 - SP804 timers
22 - I2C controller
23 - PL031 RTC
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/openbmc/u-boot/doc/
H A DREADME.rmobile4 This README is about U-Boot support for Renesas's ARM Cortex-A9 based RMOBILE[1]
5 and Cortex-A9/A53/A57 based R-Car[2] family of SoCs. Renesas's RMOBILE/R-Car SoC
6 family contains an ARM Cortex-A9/A53/A57.
12 | R8A73A0 | KMC KZM-A9-GT [3] | kzm9g_config
13 | R8A7734 | Atmark-Techno Armadillo-800-EVA [4] | armadillo-800eva_config
17 |---------------+----------------------------------------+-------------------
18 | R8A7791 M2-W | Renesas Electronics Koelsch | koelsch_defconfig
20 |---------------+----------------------------------------+-------------------
22 |---------------+----------------------------------------+-------------------
23 | R8A7793 M2-N | Renesas Electronics Gose | gose_defconfig
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/openbmc/qemu/hw/cpu/
H A Da9mpcore.c2 * Cortex-A9MPCore internal peripheral emulation.
16 #include "hw/qdev-properties.h"
18 #include "target/arm/cpu-qom.h"
26 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); in a9mp_priv_set_irq()
33 memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); in a9mp_priv_initfn()
34 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); in a9mp_priv_initfn()
36 object_initialize_child(obj, "scu", &s->scu, TYPE_A9_SCU); in a9mp_priv_initfn()
38 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); in a9mp_priv_initfn()
40 object_initialize_child(obj, "gtimer", &s->gtimer, TYPE_A9_GTIMER); in a9mp_priv_initfn()
42 object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER); in a9mp_priv_initfn()
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/openbmc/qemu/hw/arm/
H A Dxilinx_zynq.c28 #include "hw/adc/zynq-xadc.h"
31 #include "qemu/error-report.h"
36 #include "hw/qdev-clock.h"
41 #include "target/arm/cpu-qom.h"
44 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
112 rom_add_blob_fixed("board-setup", board_setup_blob, in zynq_write_board_setup()
125 object_property_set_int(OBJECT(dev), "phy-addr", 7, &error_abort); in gem_init()
144 dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); in zynq_init_spi_flashes()
145 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); in zynq_init_spi_flashes()
146 qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); in zynq_init_spi_flashes()
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H A Dnpcm7xx_boards.c25 #include "hw/qdev-core.h"
26 #include "hw/qdev-properties.h"
32 #include "system/block-backend.h"
33 #include "qemu/error-report.h"
60 const char *bios_name = machine->firmware ?: npcm7xx_default_bootrom; in npcm7xx_load_bootrom()
67 if (!machine->kernel_filename) { in npcm7xx_load_bootrom()
73 ret = load_image_mr(filename, &soc->irom); in npcm7xx_load_bootrom()
90 qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal); in npcm7xx_connect_flash()
100 object_property_set_link(OBJECT(soc), "dram-mr", OBJECT(dram), in npcm7xx_connect_dram()
109 BusState *bus = qdev_get_child_bus(DEVICE(sdhci), "sd-bus"); in sdhci_attach_drive()
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H A Dvexpress.c4 * Copyright (c) 2010 - 2011 B Labs Ltd.
20 * Contributions after 2012-01-13 are licensed under the terms of the
38 #include "qemu/error-report.h"
48 #include "target/arm/cpu-qom.h"
54 #define GIC_EXT_IRQS 64 /* Versatile Express A9 development board */
63 * the "legacy" one (used for A9) and the "Cortex-A Series"
189 #define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9")
190 #define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15")
218 unsigned int smp_cpus = ms->smp.cpus; in init_cpus()
233 if (object_property_find(cpuobj, "reset-cbar")) { in init_cpus()
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H A Drealview.c4 * Copyright (c) 2006-2007 CodeSourcery.
16 #include "hw/core/split-irq.h"
20 #include "hw/qdev-core.h"
25 #include "qemu/error-report.h"
33 #include "target/arm/cpu-qom.h"
38 #define GIC_EXT_IRQS 64 /* Realview PBX-A9 development board */
66 qdev_prop_set_uint32(splitter, "num-lines", 2); in split_irq_from_named()
93 unsigned int smp_cpus = machine->smp.cpus; in realview_init()
100 ram_addr_t ram_size = machine->ram_size; in realview_init()
121 Object *cpuobj = object_new(machine->cpu_type); in realview_init()
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/openbmc/u-boot/arch/arm/dts/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Describes the hardware common to all Zynq 7000-based boards.
6 * Copyright (C) 2011 - 2015 Xilinx
10 #address-cells = <1>;
11 #size-cells = <1>;
12 compatible = "xlnx,zynq-7000";
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
23 clock-latency = <1000>;
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H A Darmada-375.dtsi6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is dual-licensed: you can use it either under the terms
49 #include <dt-bindings/interrupt-controller/arm-gic.h>
50 #include <dt-bindings/interrupt-controller/irq.h>
51 #include <dt-bindings/phy/phy.h>
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <1000000000>;
76 compatible = "fixed-clock";
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H A Duniphier-pro5.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
9 compatible = "socionext,uniphier-pro5";
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
22 enable-method = "psci";
23 next-level-cache = <&l2>;
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H A Duniphier-ld4.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
11 compatible = "socionext,uniphier-ld4";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
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H A Duniphier-sld8.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
11 compatible = "socionext,uniphier-sld8";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
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H A Drk3xxx.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
33 compatible = "simple-bus";
34 #address-cells = <1>;
35 #size-cells = <1>;
38 dmac1_s: dma-controller@20018000 {
43 #dma-cells = <1>;
44 arm,pl330-broken-no-flushp;
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H A Dimx6q.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
24 operating-points = <
32 fsl,soc-operating-points = <
33 /* ARM kHz SOC-PU uV */
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/openbmc/u-boot/arch/arm/mach-exynos/
H A DKconfig14 Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There
33 Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and
34 Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs
44 Samsung Exynos7 SoC family are based on ARM Cortex-A57 CPU or
45 Cortex-A53 CPU (and some in a big.LITTLE configuration). There are
174 default "board/samsung/common/exynos-uboot-spl.lds" if ARCH_EXYNOS5 || ARCH_EXYNOS4
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7a/
H A Dtune-cortexa9.inc1 DEFAULTTUNE ?= "cortexa9thf-neon"
3 require conf/machine/include/arm/arch-armv7a.inc
5 TUNEVALID[cortexa9] = "Enable Cortex-A9 specific processor optimizations"
6 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexa9', ' -mcpu=cortex-a9', '', d)}"
10 AVAILTUNES += "cortexa9 cortexa9t cortexa9-neon cortexa9t-neon"
11 ARMPKGARCH:tune-cortexa9 = "cortexa9"
12 ARMPKGARCH:tune-cortexa9t = "cortexa9"
13 ARMPKGARCH:tune-cortexa9-neon = "cortexa9"
14 ARMPKGARCH:tune-cortexa9t-neon = "cortexa9"
16 TUNE_FEATURES:tune-cortexa9 = "arm vfp cortexa9"
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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/tbb/
H A Dtbb_2022.1.0.bb1 DESCRIPTION = "Parallelism library for C++ - runtime files \
2 TBB is a library that helps you leverage multi-core processor \
4 higher-level, task-based parallelism that abstracts platform details \
6 HOMEPAGE = "https://software.intel.com/en-us/tbb"
7 LICENSE = "Apache-2.0"
10 DEPENDS:append:libc-musl = " libucontext"
11 DEPENDS:append:class-target = " hwloc"
17 SRC_URI = "git://github.com/oneapi-src/oneTBB.git;protocol=https;branch=${BRANCH} \
26 -DTBB_TEST=OFF \
27 -DCMAKE_BUILD_TYPE=Release \
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/openbmc/qemu/include/hw/misc/
H A Da9scu.h2 * Cortex-A9MPCore Snoop Control Unit (SCU) emulation.
29 #define TYPE_A9_SCU "a9-scu"
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dap.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2010-2015
17 #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
23 #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
39 /* This is the main entry into U-Boot, used by the Cortex-A9 */
45 * @return SOC type - see TEGRA_SOC...
52 * @return SOC ID - see CHIPID_TEGRAxx...
59 * @return SKU ID - see SKU_ID_Txx...
63 /* Do any chip-specific cache config */
/openbmc/u-boot/arch/arm/mach-omap2/
H A DKconfig82 The AM335x high performance SOC features a Cortex-A8
92 The AM335x high performance SOC features a Cortex-A8
112 The AM43xx high performance SOC features a Cortex-A9
113 ARM core, a quad core PRU-ICSS for industrial Ethernet
130 The AM335x high performance SOC features a Cortex-A8
131 ARM core, a dual core PRU-ICSS for industrial Ethernet
149 Reserved EMIF region start address. Set to "0" to auto-select
178 boot image. For non-XIP devices, the ROM then copies the image into
181 on the device type (secure/non-secure), boot media (xip/non-xip) and
185 source "arch/arm/mach-omap2/omap3/Kconfig"
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