| /openbmc/u-boot/arch/arm/dts/ |
| H A D | armada-38x.dtsi | 55 clocks = <&coreclk 0>;
65 clocks = <&coreclk 0>;
75 clocks = <&coreclk 0>;
85 clocks = <&coreclk 0>;
95 clocks = <&coreclk 0>;
126 clocks = <&coreclk 2>;
133 clocks = <&coreclk 2>;
152 clocks = <&coreclk 0>;
163 clocks = <&coreclk 0>;
173 clocks = <&coreclk 0>;
[all …]
|
| H A D | armada-370-xp.dtsi | 95 clocks = <&coreclk 0>;
105 clocks = <&coreclk 0>;
115 clocks = <&coreclk 0>;
125 clocks = <&coreclk 0>;
135 clocks = <&coreclk 0>;
158 clocks = <&coreclk 0>;
168 clocks = <&coreclk 0>;
178 clocks = <&coreclk 0>;
188 clocks = <&coreclk 0>;
198 clocks = <&coreclk 0>;
[all …]
|
| H A D | armada-375.dtsi | 125 clocks = <&coreclk 0>;
135 clocks = <&coreclk 0>;
145 clocks = <&coreclk 0>;
155 clocks = <&coreclk 0>;
165 clocks = <&coreclk 0>;
196 clocks = <&coreclk 2>;
254 clocks = <&coreclk 0>;
266 clocks = <&coreclk 0>;
277 clocks = <&coreclk 0>;
288 clocks = <&coreclk 0>;
[all …]
|
| H A D | armada-xp.dtsi | 119 clocks = <&coreclk 0>;
131 clocks = <&coreclk 0>;
143 clocks = <&coreclk 0>;
147 coreclk: mvebu-sar@18230 { label
164 clocks = <&coreclk 1>;
173 clocks = <&coreclk 2>, <&refclk>;
179 clocks = <&coreclk 2>, <&refclk>;
|
| /openbmc/linux/arch/arm/boot/dts/marvell/ |
| H A D | armada-370-xp.dtsi | 56 clocks = <&coreclk 0>;
66 clocks = <&coreclk 0>;
76 clocks = <&coreclk 0>;
86 clocks = <&coreclk 0>;
96 clocks = <&coreclk 0>;
117 clocks = <&coreclk 0>;
126 clocks = <&coreclk 0>;
136 clocks = <&coreclk 0>;
146 clocks = <&coreclk 0>;
282 clocks = <&coreclk 0>;
[all …]
|
| H A D | armada-38x.dtsi | 56 clocks = <&coreclk 0>;
66 clocks = <&coreclk 0>;
76 clocks = <&coreclk 0>;
86 clocks = <&coreclk 0>;
96 clocks = <&coreclk 0>;
131 clocks = <&coreclk 2>;
138 clocks = <&coreclk 2>;
156 clocks = <&coreclk 0>;
166 clocks = <&coreclk 0>;
176 clocks = <&coreclk 0>;
[all …]
|
| H A D | armada-39x.dtsi | 93 clocks = <&coreclk 2>;
111 clocks = <&coreclk 0>;
121 clocks = <&coreclk 0>;
131 clocks = <&coreclk 0>;
141 clocks = <&coreclk 0>;
151 clocks = <&coreclk 0>;
161 clocks = <&coreclk 0>;
171 clocks = <&coreclk 0>;
181 clocks = <&coreclk 0>;
252 clocks = <&coreclk 0>;
[all …]
|
| H A D | armada-375.dtsi | 89 clocks = <&coreclk 0>;
99 clocks = <&coreclk 0>;
109 clocks = <&coreclk 0>;
119 clocks = <&coreclk 0>;
129 clocks = <&coreclk 0>;
159 clocks = <&coreclk 2>;
221 clocks = <&coreclk 0>;
233 clocks = <&coreclk 0>;
243 clocks = <&coreclk 0>;
253 clocks = <&coreclk 0>;
[all …]
|
| H A D | armada-xp.dtsi | 61 clocks = <&coreclk 0>;
73 clocks = <&coreclk 0>;
85 clocks = <&coreclk 0>;
89 coreclk: mvebu-sar@18230 { label
106 clocks = <&coreclk 1>;
255 clocks = <&coreclk 2>, <&refclk>;
261 clocks = <&coreclk 2>, <&refclk>;
|
| H A D | armada-370.dtsi | 136 clocks = <&coreclk 0>;
151 clocks = <&coreclk 0>;
175 clocks = <&coreclk 0>;
179 coreclk: mvebu-sar@18230 { label
313 clocks = <&coreclk 2>;
318 clocks = <&coreclk 2>;
322 clocks = <&coreclk 0>;
326 clocks = <&coreclk 0>;
|
| H A D | armada-xp-98dx3236.dtsi | 154 clocks = <&coreclk 0>;
162 clocks = <&coreclk 1>;
234 coreclk: mvebu-sar@f8204 { label
291 clocks = <&coreclk 2>, <&refclk>;
297 clocks = <&coreclk 2>, <&refclk>;
|
| H A D | armada-xp-mv78230.dtsi | 234 clocks = <&coreclk 0>;
249 clocks = <&coreclk 0>;
|
| /openbmc/linux/drivers/clk/sifive/ |
| H A D | sifive-prci.c | 304 * sifive_prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
305 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
307 * Switch the CORECLK mux to the HFCLK input source; return once complete.
324 * sifive_prci_coreclksel_use_corepll() - switch the CORECLK mux to output
326 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
328 * Switch the CORECLK mux to the COREPLL output clock; return once complete.
345 * sifive_prci_coreclksel_use_final_corepll() - switch the CORECLK mux to output
347 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
349 * Switch the CORECLK mux to the final COREPLL output clock; return once
|
| /openbmc/linux/Documentation/devicetree/bindings/timer/ |
| H A D | marvell,armada-370-xp-timer.txt | 33 clocks = <&coreclk 2>;
42 clocks = <&coreclk 2>, <&refclk>;
|
| H A D | mrvl,mmp-timer.yaml | 43 clocks = <&coreclk 2>;
|
| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | qoriq-clock.txt | 68 A second input clock, called "coreclk", may be provided if
71 - clock-names: Required if a coreclk is present. Valid names are
72 "sysclk" and "coreclk".
90 5 coreclk must be 0
|
| H A D | mvebu-cpu-clock.txt | 16 clocks = <&coreclk 1>;
|
| /openbmc/linux/drivers/pci/controller/dwc/ |
| H A D | pcie-visconti.c | 33 struct clk *coreclk; member
264 pcie->coreclk = devm_clk_get(dev, "core"); in visconti_get_resources()
265 if (IS_ERR(pcie->coreclk)) in visconti_get_resources()
266 return dev_err_probe(dev, PTR_ERR(pcie->coreclk), in visconti_get_resources()
|
| /openbmc/u-boot/drivers/clk/sifive/ |
| H A D | fu540-prci.c | 362 * __prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
363 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
365 * Switch the CORECLK mux to the HFCLK input source; return once complete.
382 * __prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL
383 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
385 * Switch the CORECLK mux to the PLL output clock; return once complete.
|
| /openbmc/linux/arch/arm64/boot/dts/freescale/ |
| H A D | fsl-ls1012a.dtsi | 68 coreclk: coreclk { label
72 clock-output-names = "coreclk";
301 clocks = <&sysclk &coreclk>;
302 clock-names = "sysclk", "coreclk";
|
| /openbmc/linux/sound/soc/fsl/ |
| H A D | fsl_esai.c | 38 * @coreclk: clock source to access register
64 struct clk *coreclk; member
984 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core"); in fsl_esai_probe()
985 if (IS_ERR(esai_priv->coreclk)) { in fsl_esai_probe()
987 PTR_ERR(esai_priv->coreclk)); in fsl_esai_probe()
988 return PTR_ERR(esai_priv->coreclk); in fsl_esai_probe()
1132 ret = clk_prepare_enable(esai->coreclk); in fsl_esai_runtime_resume()
1169 clk_disable_unprepare(esai->coreclk); in fsl_esai_runtime_resume()
1186 clk_disable_unprepare(esai->coreclk); in fsl_esai_runtime_suspend()
|
| H A D | fsl_spdif.c | 115 * @coreclk: core clock for register access via DMA
141 struct clk *coreclk; member
1598 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); in fsl_spdif_probe()
1599 if (IS_ERR(spdif_priv->coreclk)) { in fsl_spdif_probe()
1601 return PTR_ERR(spdif_priv->coreclk); in fsl_spdif_probe()
1690 clk_disable_unprepare(spdif_priv->coreclk); in fsl_spdif_runtime_suspend()
1701 ret = clk_prepare_enable(spdif_priv->coreclk); in fsl_spdif_runtime_resume()
1740 clk_disable_unprepare(spdif_priv->coreclk); in fsl_spdif_runtime_resume()
|
| /openbmc/linux/Documentation/devicetree/bindings/watchdog/ |
| H A D | moxa,moxart-watchdog.txt | 14 clocks = <&coreclk>;
|
| /openbmc/linux/drivers/clk/ |
| H A D | clk-qoriq.c | 91 struct clk *sysclk, *coreclk; member
1181 clk = input_clock_by_name(name, "coreclk"); in create_coreclk()
1186 * This indicates a mix of legacy nodes with the new coreclk in create_coreclk()
1188 * don't use the wrong input clock just because coreclk isn't in create_coreclk()
1222 if (cg->coreclk && idx != PLATFORM_PLL) { in create_one_pll()
1223 if (IS_ERR(cg->coreclk)) in create_one_pll()
1226 input = "cg-coreclk"; in create_one_pll()
1432 clk = cg->coreclk; in clockgen_clk_get()
1547 clockgen.coreclk = create_coreclk("cg-coreclk"); in _clockgen_init()
|
| /openbmc/linux/Documentation/devicetree/bindings/dma/ |
| H A D | mv-xor.txt | 32 clocks = <&coreclk 0>;
|