| /openbmc/linux/drivers/clk/ |
| H A D | clk.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
25 #include "clk.h"
54 struct clk_core *core; member
100 #include <trace/events/clk.h>
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| /openbmc/u-boot/drivers/clk/renesas/ |
| H A D | clk-rcar-gen3.c | 1 // SPDX-License-Identifier: GPL-2.0+
14 #include <clk-uclass.h>
20 #include <dt-bindings/clock/renesas-cpg-mssr.h>
22 #include "renesas-cpg-mssr.h"
23 #include "rcar-gen3-cpg.h"
62 *-------------------------------------------------------------------
88 static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk, in gen3_clk_get_parent() argument
89 struct cpg_mssr_info *info, struct clk *parent) in gen3_clk_get_parent()
91 const struct cpg_core_clk *core; in gen3_clk_get_parent() local
94 if (!renesas_clk_is_mod(clk)) { in gen3_clk_get_parent()
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| H A D | clk-rcar-gen2.c | 1 // SPDX-License-Identifier: GPL-2.0+
14 #include <clk-uclass.h>
19 #include <dt-bindings/clock/renesas-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen2-cpg.h"
60 static int gen2_clk_enable(struct clk *clk) in gen2_clk_enable() argument
62 struct gen2_clk_priv *priv = dev_get_priv(clk->dev); in gen2_clk_enable()
64 return renesas_clk_endisable(clk, priv->base, true); in gen2_clk_enable()
67 static int gen2_clk_disable(struct clk *clk) in gen2_clk_disable() argument
69 struct gen2_clk_priv *priv = dev_get_priv(clk->dev); in gen2_clk_disable()
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| H A D | renesas-cpg-mssr.c | 1 // SPDX-License-Identifier: GPL-2.0+
13 #include <clk-uclass.h>
19 #include <dt-bindings/clock/renesas-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
26 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
27 * R-Car Gen2, R-Car Gen3, and RZ/G1.
28 * These are NOT valid for R-Car Gen1 and RZ/A1!
56 #define RMSTPCR(i) (smstpcr[i] - 0x20)
64 bool renesas_clk_is_mod(struct clk *clk) in renesas_clk_is_mod() argument
66 return (clk->id >> 16) == CPG_MOD; in renesas_clk_is_mod()
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| /openbmc/linux/drivers/clk/renesas/ |
| H A D | rzg2l-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * Based on renesas-cpg-mssr.c
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/clk/renesas.h>
28 #include <linux/reset-controller.h>
32 #include <dt-bindings/clock/renesas-cpg-mssr.h>
34 #include "rzg2l-cpg.h"
85 * struct rzg2l_cpg_priv - Clock Pulse Generator Private Data
91 * @clks: Array containing all Core and Module Clocks
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| H A D | rcar-gen3-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-cpg-lib.h"
27 #include "rcar-gen3-cpg.h"
59 val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; in cpg_pll_clk_recalc_rate()
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| H A D | rcar-gen4-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen4 Clock Pulse Generator
7 * Based on rcar-gen3-cpg.c
9 * Copyright (C) 2015-2018 Glider bvba
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
23 #include "renesas-cpg-mssr.h"
24 #include "rcar-gen4-cpg.h"
25 #include "rcar-cpg-lib.h"
33 #define CPG_PLLECR_PLLST(n) BIT(8 + ((n) < 3 ? (n) - 1 : \
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| H A D | renesas-cpg-mssr.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/clk/renesas.h>
28 #include <linux/reset-controller.h>
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
33 #include "renesas-cpg-mssr.h"
34 #include "clk-div6.h"
46 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
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| H A D | rcar-gen2-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen2 Clock Pulse Generator
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
18 #include "renesas-cpg-mssr.h"
19 #include "rcar-gen2-cpg.h"
39 * prepare - clk_prepare only ensures that parents are prepared
40 * enable - clk_enable only ensures that parents are enabled
41 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
42 * parent - fixed parent. No clk_set_parent support
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| /openbmc/linux/drivers/clk/microchip/ |
| H A D | clk-pic32mzda.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/clock/microchip,pic32-clock.h>
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
17 #include "clk-core.h"
81 .slew_div = 2, /* step of div_4 -> div_2 -> no_div */
128 struct clk *clks[MAXCLKS];
129 struct pic32_clk_common core; member
142 if (readl(cd->core.iobase) & BIT(2)) in pic32_fscm_nmi()
143 pr_alert("pic32-clk: FSCM detected clk failure.\n"); in pic32_fscm_nmi()
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| H A D | clk-core.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
12 #include <asm/mach-pic32/pic32.h>
15 #include "clk-core.h"
78 /* add instruction pipeline delay while CPU clock is in-transition. */
92 struct pic32_clk_common *core; member
101 return readl(pb->ctrl_reg) & PB_DIV_ENABLE; in pbclk_is_enabled()
108 writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg)); in pbclk_enable()
116 writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg)); in pbclk_disable()
137 if (abs(rate - divided_rate_down) < abs(rate - divided_rate)) in calc_best_divided_rate()
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| H A D | clk-core.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
65 struct clk *pic32_periph_clk_register(const struct pic32_periph_clk_data *data,
66 struct pic32_clk_common *core);
67 struct clk *pic32_refo_clk_register(const struct pic32_ref_osc_data *data,
68 struct pic32_clk_common *core);
69 struct clk *pic32_sys_clk_register(const struct pic32_sys_clk_data *data,
70 struct pic32_clk_common *core);
71 struct clk *pic32_spll_clk_register(const struct pic32_sys_pll_data *data,
72 struct pic32_clk_common *core);
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| /openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | mcp77.c | 42 read_div(struct mcp77_clk *clk) in read_div() argument
44 struct nvkm_device *device = clk->base.subdev.device; in read_div()
49 read_pll(struct mcp77_clk *clk, u32 base) in read_pll() argument
51 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll()
83 struct mcp77_clk *clk = mcp77_clk(base); in mcp77_clk_read() local
84 struct nvkm_subdev *subdev = &clk->base.subdev; in mcp77_clk_read()
85 struct nvkm_device *device = subdev->device; in mcp77_clk_read()
91 return device->crystal; in mcp77_clk_read()
95 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 4; in mcp77_clk_read()
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| /openbmc/linux/include/trace/events/ |
| H A D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #define TRACE_SYSTEM clk
15 DECLARE_EVENT_CLASS(clk,
17 TP_PROTO(struct clk_core *core),
19 TP_ARGS(core),
22 __string( name, core->name )
26 __assign_str(name, core->name);
32 DEFINE_EVENT(clk, clk_enable,
34 TP_PROTO(struct clk_core *core),
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| /openbmc/linux/arch/arm64/boot/dts/marvell/ |
| H A D | armada-cp11x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
42 cooling-maps { };
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| /openbmc/linux/arch/arm/mach-omap2/ |
| H A D | omap_hwmod_2xxx_interconnect_data.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
5 * Copyright (C) 2009-2011 Nokia Corporation
9 * XXX these should be marked initdata for multi-OMAP kernels
23 /* L3 -> L4_CORE interface */
30 /* MPU -> L3 interface */
37 /* DSS -> l3 */
50 /* L4_CORE -> L4_WKUP interface */
57 /* L4 CORE -> UART1 interface */
61 .clk = "uart1_ick",
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| /openbmc/linux/arch/mips/lantiq/falcon/ |
| H A D | sysctrl.c | 1 // SPDX-License-Identifier: GPL-2.0-only
16 #include "../clk.h"
80 static inline void sysctl_wait(struct clk *clk, in sysctl_wait() argument
85 do {} while (--err && ((sysctl_r32(clk->module, reg) in sysctl_wait()
86 & clk->bits) != test)); in sysctl_wait()
89 clk->module, clk->bits, test, in sysctl_wait()
90 sysctl_r32(clk->module, reg) & clk->bits); in sysctl_wait()
93 static int sysctl_activate(struct clk *clk) in sysctl_activate() argument
95 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); in sysctl_activate()
96 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); in sysctl_activate()
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| /openbmc/linux/drivers/net/ipa/ |
| H A D | ipa_power.c | 1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2022 Linaro Ltd.
7 #include <linux/clk.h>
25 * The IPA hardware is enabled when the IPA core clock and all the
27 * management is used to determine whether the core clock and
31 * The core clock currently runs at a fixed clock rate when enabled,
38 * enum ipa_power_flag - IPA power flags
54 * struct ipa_power - IPA power management information
56 * @core: IPA core clock
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| /openbmc/linux/drivers/remoteproc/ |
| H A D | st_slim_rproc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SLIM core rproc driver
10 #include <linux/clk.h>
20 /* SLIM core registers */
59 int clk, err; in slim_clk_get() local
61 for (clk = 0; clk < ST_SLIM_MAX_CLK; clk++) { in slim_clk_get()
62 slim_rproc->clks[clk] = of_clk_get(dev->of_node, clk); in slim_clk_get()
63 if (IS_ERR(slim_rproc->clks[clk])) { in slim_clk_get()
64 err = PTR_ERR(slim_rproc->clks[clk]); in slim_clk_get()
65 if (err == -EPROBE_DEFER) in slim_clk_get()
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| /openbmc/linux/Documentation/devicetree/bindings/arm/marvell/ |
| H A D | cp110-system-controller.txt | 4 The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K
6 giving access to numerous features: clocks, pin-muxing and many other
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the CP110 system controller
18 -------
23 - a set of core clocks
24 - a set of gateable clocks
28 - The first cell must be 0 or 1. 0 for the core clocks and 1 for the
30 - The second cell identifies the particular core clock or gateable
34 - Core clocks
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| /openbmc/u-boot/include/ |
| H A D | clk-uclass.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
11 /* See clk.h for background documentation. */
13 #include <clk.h>
18 * struct clk_ops - The functions that a clock driver must implement.
22 * of_xlate - Translate a client's device-tree (OF) clock specifier.
24 * The clock core calls this function as the first step in implementing
27 * If this function pointer is set to NULL, the clock core will use a
28 * default implementation, which assumes #clock-cells = <1>, and that
31 * At present, the clock API solely supports device-tree. If this
39 int (*of_xlate)(struct clk *clock,
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| /openbmc/linux/Documentation/devicetree/bindings/media/ |
| H A D | nxp,imx8mq-mipi-csi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MQ MIPI CSI-2 receiver
10 - Martin Kepplinger <martin.kepplinger@puri.sm>
12 description: |-
13 This binding covers the CSI-2 RX PHY and host controller included in the
20 - fsl,imx8mq-mipi-csi2
27 - description: core is the RX Controller Core Clock input. This clock
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| /openbmc/linux/drivers/clk/versatile/ |
| H A D | clk-versatile.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include "clk-icst.h"
20 /* Base offset for the core module */
59 struct clk *clk; in cm_osc_setup() local
60 const char *clk_name = np->name; in cm_osc_setup()
64 /* Remap the core module base if not done yet */ in cm_osc_setup()
69 pr_err("no parent on core module clock\n"); in cm_osc_setup()
75 pr_err("could not remap core module base\n"); in cm_osc_setup()
81 clk = icst_clk_register(NULL, desc, clk_name, parent_name, cm_base); in cm_osc_setup()
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| /openbmc/linux/Documentation/devicetree/bindings/sound/ |
| H A D | fsl,rpmsg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
14 are SAI, MICFIL, DMA controlled by Cortex M core. What we see from
18 Cortex-A and Cortex-M.
21 - $ref: sound-card-common.yaml#
26 - fsl,imx7ulp-rpmsg-audio
27 - fsl,imx8mn-rpmsg-audio
28 - fsl,imx8mm-rpmsg-audio
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| /openbmc/linux/Documentation/devicetree/bindings/soc/imx/ |
| H A D | fsl,imx8mm-disp-blk-ctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
20 - const: fsl,imx8mm-disp-blk-ctrl
21 - const: syscon
26 '#power-domain-cells':
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