| /openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/ |
| H A D | StorageControllerMetrics.v1_1_0.json | 4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2025 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
28 "description": "The available OEM-specific actions for this resource.",
29 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
37 …"longDescription": "The object shall contain the NVMe-defined 'Endurance Group Critical Warning Su…
39 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
54 …indication of whether namespaces in one or more Endurance Groups are in read-only mode not as a re…
55 …hall indicate whether namespaces in one or more Endurance Groups are in read-only mode not as a re…
63 …ability of one or more Endurance Groups is degraded due to significant media-related errors or any…
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| H A D | StorageController.v1_10_0.json | 4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2025 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
15 …ces in this group are inaccessible. Commands are not able to access user data of namespaces in th…
16 …essed by a controller that reports this state for an ANA group provide non-optimized access charac…
17 …"Optimized": "Commands processed by a controller provide optimized access to any namespace in the …
18 …istently inaccessible. Commands are persistently not able to access user data of namespaces in th…
24 … "description": "The ANA characteristics and volume information for a storage controller.",
25 …"This type shall contain the ANA characteristics and volume information for a storage controller.",
27 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
68 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
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| /openbmc/u-boot/include/ |
| H A D | syscon.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
14 * struct syscon_uc_info - Information stored by the syscon UCLASS_UCLASS
16 * @regmap: Register map for this controller
26 #define syscon_get_ops(dev) ((struct syscon_ops *)(dev)->driver->ops)
30 * We don't support 64-bit machines. If they are so resource-contrained that
34 * Update: 64-bit is now supported and we have an education crisis.
42 * syscon_get_regmap() - Get access to a register map
46 * @return 0 if OK, -ve on error
51 * syscon_get_regmap_by_driver_data() - Look up a controller by its ID
53 * Each system controller can be accessed by its driver data, which is
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| H A D | nvme.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
13 * nvme_identify - identify controller or namespace capabilities and status
15 * This issues an identify command to the NVMe controller to return a data
16 * buffer that describes the controller or namespace capabilities and status.
18 * @dev: NVMe controller device
19 * @nsid: 0 for controller, namespace id for namespace to identify
20 * @cns: 1 for controller, 0 for namespace
22 * @return: 0 on success, -ETIMEDOUT on command execution timeout,
23 * -EIO on command execution fails
29 * nvme_get_features - retrieve the attributes of the feature specified
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| /openbmc/qemu/hw/display/ |
| H A D | vga_regs.h | 2 * linux/include/video/vga.h -- standard VGA chipset interaction
22 /* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */
28 /* Multi-chipset support Copyright 1993 Harm Hanemaayer */
31 /* VGA data register ports */
32 #define VGA_CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */
33 #define VGA_CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */
34 #define VGA_ATT_R 0x3C1 /* Attribute Controller Data Read Register */
35 #define VGA_ATT_W 0x3C0 /* Attribute Controller Data Write Register */
36 #define VGA_GFX_D 0x3CF /* Graphics Controller Data Register */
37 #define VGA_SEQ_D 0x3C5 /* Sequencer Data Register */
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| /openbmc/bmcweb/redfish-core/schema/dmtf/json-schema-installed/ |
| H A D | StorageController.v1_10_0.json | 4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2025 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
15 …ces in this group are inaccessible. Commands are not able to access user data of namespaces in th…
16 …essed by a controller that reports this state for an ANA group provide non-optimized access charac…
17 …"Optimized": "Commands processed by a controller provide optimized access to any namespace in the …
18 …istently inaccessible. Commands are persistently not able to access user data of namespaces in th…
24 … "description": "The ANA characteristics and volume information for a storage controller.",
25 …"This type shall contain the ANA characteristics and volume information for a storage controller.",
27 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
68 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
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| /openbmc/bmcweb/redfish-core/include/registries/ |
| H A D | storage_device_message_registry.hpp | 1 // SPDX-License-Identifier: Apache-2.0
2 // SPDX-FileCopyrightText: Copyright OpenBMC Authors
6 * This is an auto-generated header which contains definitions
18 // clang-format off
25 "Copyright 2020-2023 DMTF. All rights reserved.",
93 "A storage controller degraded condition was detected.",
94 …"A degraded condition for the storage controller located in '%1' was detected due to reason '%2'.",
101 …the storage controller in the PCI slot. Update the controller to the latest firmware version. If…
106 "A storage controller failure was detected.",
107 "A failure condition for the storage controller located in '%1' was detected.",
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| /openbmc/u-boot/arch/nds32/include/asm/arch-ag102/ |
| H A D | ag102.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
14 /* PCI Controller */
16 /* LPC Controller */
18 /* LPC Controller */
21 /* NDS32 Data Local Memory 01 */
23 /* NDS32 Data Local Memory 02 */
26 /* Synopsys DWC DDR2/1 Controller */
28 /* DMA Controller */
30 /* FTIDE020_S IDE (ATA) Controller */
32 /* USB OTG Controller */
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| /openbmc/bmcweb/redfish-core/schema/dmtf/csdl/ |
| H A D | StorageControllerMetrics_v1.xml | 1 <?xml version="1.0" encoding="UTF-8"?>
2 <!---->
3 <!--################################################################################ …
4 <!--# Redfish Schema: StorageControllerMetrics v1.1.0 …
5 <!--# …
6 <!--# For a detailed change log, see the README file contained in the DSP8010 bundle, …
7 <!--# available at http://www.dmtf.org/standards/redfish …
8 <!--# Copyright 2014-2025 DMTF in cooperation with Storage Networking Industry Association (SNIA). …
9 <!--# For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright …
10 <!--################################################################################ …
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| H A D | StorageController_v1.xml | 1 <?xml version="1.0" encoding="UTF-8"?>
2 <!---->
3 <!--################################################################################ -->
4 <!--# Redfish Schema: StorageController v1.10.0 -->
5 <!--# -->
6 <!--# For a detailed change log, see the README file contained in the DSP8010 bundle, -->
7 <!--# available at http://www.dmtf.org/standards/redfish -->
8 <!--# Copyright 2014-2025 DMTF. -->
9 <!--# For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright -->
10 <!--################################################################################ -->
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| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.soc | 13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
30 - Cryptography acceleration (SEC)
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| /openbmc/u-boot/drivers/pinctrl/exynos/ |
| H A D | pinctrl-exynos.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
12 #define PIN_DAT 0x04 /* Offset of pin data register */
17 * struct samsung_pin_bank_data: represent a controller pin-bank data.
18 * @offset: starting offset of the pin-bank registers.
36 * struct samsung_pin_ctrl: represent a pin controller.
37 * @pin_banks: list of pin banks included in this controller.
46 * struct exynos_pinctrl_priv: exynos pin controller driver private data
47 * @pin_ctrl: pin controller bank information.
48 * @base: base address of the pin controller instance.
49 * @num_banks: number of pin banks included in the pin controller.
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| H A D | pinctrl-exynos7420.c | 1 // SPDX-License-Identifier: GPL-2.0+
16 #include "pinctrl-exynos.h"
36 unsigned long base = priv->base; in exynos7420_pinctrl_request()
44 return -ENODEV; in exynos7420_pinctrl_request()
55 /* pin banks of Exynos7420 pin-controller - BUS0 */
74 /* pin banks of Exynos7420 pin-controller - FSYS0 */
79 /* pin banks of Exynos7420 pin-controller - FSYS1 */
89 /* pin-controller instance BUS0 data */
93 /* pin-controller instance FSYS0 data */
97 /* pin-controller instance FSYS1 data */
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| /openbmc/qemu/tests/qtest/ |
| H A D | remote-i3c-test.c | |
| /openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | sama5d2.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Chip-specific header file for the SAMA5D2 SoC
21 #define ATMEL_ID_XDMAC0 6 /* DMA Controller 0 */
22 #define ATMEL_ID_XDMAC1 7 /* DMA Controller 1 */
26 #define ATMEL_ID_TDES 11 /* Triple Data Encryption Standard */
28 #define ATMEL_ID_MPDDRC 13 /* MPDDR Controller */
29 #define ATMEL_ID_MATRIX1 14 /* H32MX, 32-bit AHB Matrix */
30 #define ATMEL_ID_MATRIX0 15 /* H64MX, 64-bit AHB Matrix */
32 #define ATMEL_ID_HSMC 17 /* Multi-bit ECC interrupt */
33 #define ATMEL_ID_PIOA 18 /* Parallel I/O Controller A */
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| /openbmc/u-boot/doc/driver-model/ |
| H A D | usb-info.txt | 5 ------------
9 understand how things work with USB in U-Boot when driver model is enabled.
13 -----------------------------
22 -------------------------
28 { .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 },
29 { .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 },
30 { .compatible = "nvidia,tegra114-ehci", .data = USB_CTLR_T114 },
48 Each has its own data value. Controllers must be in the UCLASS_USB uclass.
50 The ofdata_to_platdata() method allows the controller driver to grab any
54 most cases, since they are all EHCI-compatible. For EHCI there are also some
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | lpc32xx_nand_mlc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * LPC32xx MLC NAND flash controller driver
10 * The MLC NAND flash controller provides hardware Reed-Solomon ECC
11 * covering in- and out-of-band data together. Therefore, in- and out-
12 * of-band data must be written together in order to have a valid ECC.
14 * Consequently, pages with meaningful in-band data are written with
15 * blank (all-ones) out-of-band data and a valid ECC, and any later
16 * out-of-band data write will void the ECC.
18 * Therefore, code which reads such late-written out-of-band data
31 * MLC NAND controller registers.
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| H A D | Kconfig | 9 This option, if enabled, provides more flexible and linux-like
19 bool "Support Atmel NAND controller"
23 controller.
36 The Programmable Multibit ECC (PMECC) controller is a programmable
64 bool "Support TI Davinci NAND controller"
75 bool "Support Denali NAND controller as a DT device"
80 controller as a DT device.
88 of OOB area before last ECC sector data starts. This is potentially
92 bool "Support LPC32XX_SLC controller"
94 Enable the LPC32XX SLC NAND controller.
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| /openbmc/qemu/docs/system/devices/ |
| H A D | nvme.rst | 5 QEMU provides NVMe emulation through the ``nvme``, ``nvme-ns`` and
6 ``nvme-subsys`` devices.
11 * Configuration of `Optional Features`_ such as `Controller Memory Buffer`_,
12 `Simple Copy`_, `Zoned Namespaces`_, `metadata`_ and `End-to-End Data
18 Controller Emulation
19 --------------------
21 The QEMU emulated NVMe controller implements version 1.4 of the NVM Express
29 The simplest way to attach an NVMe controller on the QEMU PCI bus is to add the
32 .. code-block:: console
34 -drive file=nvm.img,if=none,id=nvm
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| /openbmc/u-boot/doc/ |
| H A D | I2C_Edge_Conditions | 5 and the CPU was reset. This may result in EEPROM data corruption.
9 2) I2C controller issues a start command.
14 1) The I2C controller issues a start command.
15 2) The I2C controller writes the device address.
16 3) The I2C controller writes the offset.
23 5) Offset in device, "EEPROM interprets this as data to write"
27 as data to be written in location "device address".
30 -----
34 controller and device available. For boards where a I2C bus reset
38 bit-banging I2C driver (common/soft_i2c.c) as this already includes
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| /openbmc/u-boot/drivers/mmc/ |
| H A D | pxa_mmc_gen.c | 1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/regs-mmc.h>
52 struct pxa_mmc_priv *priv = mmc->priv; in pxa_mmc_wait()
53 struct pxa_mmc_regs *regs = priv->regs; in pxa_mmc_wait()
57 while (--timeout) { in pxa_mmc_wait()
58 if (readl(®s->stat) & mask) in pxa_mmc_wait()
64 return -ETIMEDOUT; in pxa_mmc_wait()
71 struct pxa_mmc_priv *priv = mmc->priv; in pxa_mmc_stop_clock()
72 struct pxa_mmc_regs *regs = priv->regs; in pxa_mmc_stop_clock()
76 if (!(readl(®s->stat) & MMC_STAT_CLK_EN)) in pxa_mmc_stop_clock()
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| /openbmc/bmcweb/redfish-core/schema/dmtf/installed/ |
| H A D | StorageController_v1.xml | 1 <?xml version="1.0" encoding="UTF-8"?>
2 <!---->
3 <!--################################################################################ -->
4 <!-
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| /openbmc/u-boot/drivers/i2c/ |
| H A D | mvtwsi.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for the TWSI (i2c) controller found on the Marvell
56 u32 data; member
68 u32 data; member
87 /* Number of the device (determined from cell-index property) */
99 * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control
118 * On sun6i and newer, IFLG is a write-clear bit, which is cleared by writing 1;
129 * enum mvstwsi_status_values - Possible values of I2C controller's status
133 * non-10-bit-address devices are specified.
146 /* Data transmitted, ACK received */
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| /openbmc/u-boot/drivers/usb/musb-new/ |
| H A D | am35x.c | 1 // SPDX-License-Identifier: GPL-2.0
8 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
10 * This file is part of the Inventra Controller Driver for Linux.
21 #include <linux/dma-mapping.h>
27 #include "linux-compat.h"
83 #define glue_to_musb(g) platform_get_drvdata(g->musb)
86 * am35x_musb_enable - enable interrupts
94 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_enable()
98 epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) | in am35x_musb_enable()
99 ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT); in am35x_musb_enable()
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| /openbmc/u-boot/drivers/sysreset/ |
| H A D | sysreset-ti-sci.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
16 * struct ti_sci_sysreset_data - sysreset controller information structure
17 * @sci: TI SCI handle used for communication with system controller
25 struct ti_sci_sysreset_data *data = dev_get_priv(dev); in ti_sci_sysreset_probe() local
29 if (!data) in ti_sci_sysreset_probe()
30 return -ENOMEM; in ti_sci_sysreset_probe()
32 /* Store handle for communication with the system controller */ in ti_sci_sysreset_probe()
33 data->sci = ti_sci_get_handle(dev); in ti_sci_sysreset_probe()
34 if (IS_ERR(data->sci)) in ti_sci_sysreset_probe()
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