1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
207133f2eSMarek Vasut /*
307133f2eSMarek Vasut * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
407133f2eSMarek Vasut *
507133f2eSMarek Vasut * Loosely based on the old code and Linux's PXA MMC driver
607133f2eSMarek Vasut */
707133f2eSMarek Vasut
807133f2eSMarek Vasut #include <common.h>
907133f2eSMarek Vasut #include <asm/arch/hardware.h>
1007133f2eSMarek Vasut #include <asm/arch/regs-mmc.h>
111221ce45SMasahiro Yamada #include <linux/errno.h>
1207133f2eSMarek Vasut #include <asm/io.h>
1354a5cf81SMarcel Ziswiler #include <malloc.h>
1454a5cf81SMarcel Ziswiler #include <mmc.h>
1507133f2eSMarek Vasut
1607133f2eSMarek Vasut /* PXAMMC Generic default config for various CPUs */
17abc20abaSMarek Vasut #if defined(CONFIG_CPU_PXA25X)
1807133f2eSMarek Vasut #define PXAMMC_FIFO_SIZE 1
1907133f2eSMarek Vasut #define PXAMMC_MIN_SPEED 312500
2007133f2eSMarek Vasut #define PXAMMC_MAX_SPEED 20000000
2107133f2eSMarek Vasut #define PXAMMC_HOST_CAPS (0)
22abc20abaSMarek Vasut #elif defined(CONFIG_CPU_PXA27X)
2307133f2eSMarek Vasut #define PXAMMC_CRC_SKIP
2407133f2eSMarek Vasut #define PXAMMC_FIFO_SIZE 32
2507133f2eSMarek Vasut #define PXAMMC_MIN_SPEED 304000
2607133f2eSMarek Vasut #define PXAMMC_MAX_SPEED 19500000
2707133f2eSMarek Vasut #define PXAMMC_HOST_CAPS (MMC_MODE_4BIT)
2807133f2eSMarek Vasut #elif defined(CONFIG_CPU_MONAHANS)
2907133f2eSMarek Vasut #define PXAMMC_FIFO_SIZE 32
3007133f2eSMarek Vasut #define PXAMMC_MIN_SPEED 304000
3107133f2eSMarek Vasut #define PXAMMC_MAX_SPEED 26000000
3207133f2eSMarek Vasut #define PXAMMC_HOST_CAPS (MMC_MODE_4BIT | MMC_MODE_HS)
3307133f2eSMarek Vasut #else
3407133f2eSMarek Vasut #error "This CPU isn't supported by PXA MMC!"
3507133f2eSMarek Vasut #endif
3607133f2eSMarek Vasut
3707133f2eSMarek Vasut #define MMC_STAT_ERRORS \
3807133f2eSMarek Vasut (MMC_STAT_RES_CRC_ERROR | MMC_STAT_SPI_READ_ERROR_TOKEN | \
3907133f2eSMarek Vasut MMC_STAT_CRC_READ_ERROR | MMC_STAT_TIME_OUT_RESPONSE | \
4007133f2eSMarek Vasut MMC_STAT_READ_TIME_OUT | MMC_STAT_CRC_WRITE_ERROR)
4107133f2eSMarek Vasut
4207133f2eSMarek Vasut /* 1 millisecond (in wait cycles below it's 100 x 10uS waits) */
4307133f2eSMarek Vasut #define PXA_MMC_TIMEOUT 100
4407133f2eSMarek Vasut
4507133f2eSMarek Vasut struct pxa_mmc_priv {
4607133f2eSMarek Vasut struct pxa_mmc_regs *regs;
4707133f2eSMarek Vasut };
4807133f2eSMarek Vasut
4907133f2eSMarek Vasut /* Wait for bit to be set */
pxa_mmc_wait(struct mmc * mmc,uint32_t mask)5007133f2eSMarek Vasut static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask)
5107133f2eSMarek Vasut {
5293bfd616SPantelis Antoniou struct pxa_mmc_priv *priv = mmc->priv;
5307133f2eSMarek Vasut struct pxa_mmc_regs *regs = priv->regs;
5407133f2eSMarek Vasut unsigned int timeout = PXA_MMC_TIMEOUT;
5507133f2eSMarek Vasut
5607133f2eSMarek Vasut /* Wait for bit to be set */
5707133f2eSMarek Vasut while (--timeout) {
5807133f2eSMarek Vasut if (readl(®s->stat) & mask)
5907133f2eSMarek Vasut break;
6007133f2eSMarek Vasut udelay(10);
6107133f2eSMarek Vasut }
6207133f2eSMarek Vasut
6307133f2eSMarek Vasut if (!timeout)
6407133f2eSMarek Vasut return -ETIMEDOUT;
6507133f2eSMarek Vasut
6607133f2eSMarek Vasut return 0;
6707133f2eSMarek Vasut }
6807133f2eSMarek Vasut
pxa_mmc_stop_clock(struct mmc * mmc)6907133f2eSMarek Vasut static int pxa_mmc_stop_clock(struct mmc *mmc)
7007133f2eSMarek Vasut {
7193bfd616SPantelis Antoniou struct pxa_mmc_priv *priv = mmc->priv;
7207133f2eSMarek Vasut struct pxa_mmc_regs *regs = priv->regs;
7307133f2eSMarek Vasut unsigned int timeout = PXA_MMC_TIMEOUT;
7407133f2eSMarek Vasut
7507133f2eSMarek Vasut /* If the clock aren't running, exit */
7607133f2eSMarek Vasut if (!(readl(®s->stat) & MMC_STAT_CLK_EN))
7707133f2eSMarek Vasut return 0;
7807133f2eSMarek Vasut
7907133f2eSMarek Vasut /* Tell the controller to turn off the clock */
8007133f2eSMarek Vasut writel(MMC_STRPCL_STOP_CLK, ®s->strpcl);
8107133f2eSMarek Vasut
8207133f2eSMarek Vasut /* Wait until the clock are off */
8307133f2eSMarek Vasut while (--timeout) {
8407133f2eSMarek Vasut if (!(readl(®s->stat) & MMC_STAT_CLK_EN))
8507133f2eSMarek Vasut break;
8607133f2eSMarek Vasut udelay(10);
8707133f2eSMarek Vasut }
8807133f2eSMarek Vasut
8907133f2eSMarek Vasut /* The clock refused to stop, scream and die a painful death */
9007133f2eSMarek Vasut if (!timeout)
9107133f2eSMarek Vasut return -ETIMEDOUT;
9207133f2eSMarek Vasut
9307133f2eSMarek Vasut /* The clock stopped correctly */
9407133f2eSMarek Vasut return 0;
9507133f2eSMarek Vasut }
9607133f2eSMarek Vasut
pxa_mmc_start_cmd(struct mmc * mmc,struct mmc_cmd * cmd,uint32_t cmdat)9707133f2eSMarek Vasut static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
9807133f2eSMarek Vasut uint32_t cmdat)
9907133f2eSMarek Vasut {
10093bfd616SPantelis Antoniou struct pxa_mmc_priv *priv = mmc->priv;
10107133f2eSMarek Vasut struct pxa_mmc_regs *regs = priv->regs;
10207133f2eSMarek Vasut int ret;
10307133f2eSMarek Vasut
10407133f2eSMarek Vasut /* The card can send a "busy" response */
10595b01c47SAndy Fleming if (cmd->resp_type & MMC_RSP_BUSY)
10607133f2eSMarek Vasut cmdat |= MMC_CMDAT_BUSY;
10707133f2eSMarek Vasut
10807133f2eSMarek Vasut /* Inform the controller about response type */
10907133f2eSMarek Vasut switch (cmd->resp_type) {
11007133f2eSMarek Vasut case MMC_RSP_R1:
11107133f2eSMarek Vasut case MMC_RSP_R1b:
11207133f2eSMarek Vasut cmdat |= MMC_CMDAT_R1;
11307133f2eSMarek Vasut break;
11407133f2eSMarek Vasut case MMC_RSP_R2:
11507133f2eSMarek Vasut cmdat |= MMC_CMDAT_R2;
11607133f2eSMarek Vasut break;
11707133f2eSMarek Vasut case MMC_RSP_R3:
11807133f2eSMarek Vasut cmdat |= MMC_CMDAT_R3;
11907133f2eSMarek Vasut break;
12007133f2eSMarek Vasut default:
12107133f2eSMarek Vasut break;
12207133f2eSMarek Vasut }
12307133f2eSMarek Vasut
12407133f2eSMarek Vasut /* Load command and it's arguments into the controller */
12507133f2eSMarek Vasut writel(cmd->cmdidx, ®s->cmd);
12607133f2eSMarek Vasut writel(cmd->cmdarg >> 16, ®s->argh);
12707133f2eSMarek Vasut writel(cmd->cmdarg & 0xffff, ®s->argl);
12807133f2eSMarek Vasut writel(cmdat, ®s->cmdat);
12907133f2eSMarek Vasut
13007133f2eSMarek Vasut /* Start the controller clock and wait until they are started */
13107133f2eSMarek Vasut writel(MMC_STRPCL_START_CLK, ®s->strpcl);
13207133f2eSMarek Vasut
13307133f2eSMarek Vasut ret = pxa_mmc_wait(mmc, MMC_STAT_CLK_EN);
13407133f2eSMarek Vasut if (ret)
13507133f2eSMarek Vasut return ret;
13607133f2eSMarek Vasut
13707133f2eSMarek Vasut /* Correct and happy end */
13807133f2eSMarek Vasut return 0;
13907133f2eSMarek Vasut }
14007133f2eSMarek Vasut
pxa_mmc_cmd_done(struct mmc * mmc,struct mmc_cmd * cmd)14107133f2eSMarek Vasut static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd)
14207133f2eSMarek Vasut {
14393bfd616SPantelis Antoniou struct pxa_mmc_priv *priv = mmc->priv;
14407133f2eSMarek Vasut struct pxa_mmc_regs *regs = priv->regs;
14507133f2eSMarek Vasut uint32_t a, b, c;
14607133f2eSMarek Vasut int i;
14707133f2eSMarek Vasut int stat;
14807133f2eSMarek Vasut
14907133f2eSMarek Vasut /* Read the controller status */
15007133f2eSMarek Vasut stat = readl(®s->stat);
15107133f2eSMarek Vasut
15207133f2eSMarek Vasut /*
15307133f2eSMarek Vasut * Linux says:
15407133f2eSMarek Vasut * Did I mention this is Sick. We always need to
15507133f2eSMarek Vasut * discard the upper 8 bits of the first 16-bit word.
15607133f2eSMarek Vasut */
15707133f2eSMarek Vasut a = readl(®s->res) & 0xffff;
15807133f2eSMarek Vasut for (i = 0; i < 4; i++) {
15907133f2eSMarek Vasut b = readl(®s->res) & 0xffff;
16007133f2eSMarek Vasut c = readl(®s->res) & 0xffff;
16107133f2eSMarek Vasut cmd->response[i] = (a << 24) | (b << 8) | (c >> 8);
16207133f2eSMarek Vasut a = c;
16307133f2eSMarek Vasut }
16407133f2eSMarek Vasut
16507133f2eSMarek Vasut /* The command response didn't arrive */
16607133f2eSMarek Vasut if (stat & MMC_STAT_TIME_OUT_RESPONSE)
16707133f2eSMarek Vasut return -ETIMEDOUT;
16895b01c47SAndy Fleming else if (stat & MMC_STAT_RES_CRC_ERROR
16995b01c47SAndy Fleming && cmd->resp_type & MMC_RSP_CRC) {
17007133f2eSMarek Vasut #ifdef PXAMMC_CRC_SKIP
17195b01c47SAndy Fleming if (cmd->resp_type & MMC_RSP_136
17295b01c47SAndy Fleming && cmd->response[0] & (1 << 31))
17307133f2eSMarek Vasut printf("Ignoring CRC, this may be dangerous!\n");
17407133f2eSMarek Vasut else
17507133f2eSMarek Vasut #endif
17607133f2eSMarek Vasut return -EILSEQ;
17707133f2eSMarek Vasut }
17807133f2eSMarek Vasut
17907133f2eSMarek Vasut /* The command response was successfully read */
18007133f2eSMarek Vasut return 0;
18107133f2eSMarek Vasut }
18207133f2eSMarek Vasut
pxa_mmc_do_read_xfer(struct mmc * mmc,struct mmc_data * data)18307133f2eSMarek Vasut static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data)
18407133f2eSMarek Vasut {
18593bfd616SPantelis Antoniou struct pxa_mmc_priv *priv = mmc->priv;
18607133f2eSMarek Vasut struct pxa_mmc_regs *regs = priv->regs;
18707133f2eSMarek Vasut uint32_t len;
18807133f2eSMarek Vasut uint32_t *buf = (uint32_t *)data->dest;
18907133f2eSMarek Vasut int size;
19007133f2eSMarek Vasut int ret;
19107133f2eSMarek Vasut
19207133f2eSMarek Vasut len = data->blocks * data->blocksize;
19307133f2eSMarek Vasut
19407133f2eSMarek Vasut while (len) {
19507133f2eSMarek Vasut /* The controller has data ready */
19607133f2eSMarek Vasut if (readl(®s->i_reg) & MMC_I_REG_RXFIFO_RD_REQ) {
197b4141195SMasahiro Yamada size = min(len, (uint32_t)PXAMMC_FIFO_SIZE);
19807133f2eSMarek Vasut len -= size;
19907133f2eSMarek Vasut size /= 4;
20007133f2eSMarek Vasut
20107133f2eSMarek Vasut /* Read data into the buffer */
20207133f2eSMarek Vasut while (size--)
20307133f2eSMarek Vasut *buf++ = readl(®s->rxfifo);
20407133f2eSMarek Vasut
20507133f2eSMarek Vasut }
20607133f2eSMarek Vasut
20707133f2eSMarek Vasut if (readl(®s->stat) & MMC_STAT_ERRORS)
20807133f2eSMarek Vasut return -EIO;
20907133f2eSMarek Vasut }
21007133f2eSMarek Vasut
21107133f2eSMarek Vasut /* Wait for the transmission-done interrupt */
21207133f2eSMarek Vasut ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
21307133f2eSMarek Vasut if (ret)
21407133f2eSMarek Vasut return ret;
21507133f2eSMarek Vasut
21607133f2eSMarek Vasut return 0;
21707133f2eSMarek Vasut }
21807133f2eSMarek Vasut
pxa_mmc_do_write_xfer(struct mmc * mmc,struct mmc_data * data)21907133f2eSMarek Vasut static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data)
22007133f2eSMarek Vasut {
22193bfd616SPantelis Antoniou struct pxa_mmc_priv *priv = mmc->priv;
22207133f2eSMarek Vasut struct pxa_mmc_regs *regs = priv->regs;
22307133f2eSMarek Vasut uint32_t len;
22407133f2eSMarek Vasut uint32_t *buf = (uint32_t *)data->src;
22507133f2eSMarek Vasut int size;
22607133f2eSMarek Vasut int ret;
22707133f2eSMarek Vasut
22807133f2eSMarek Vasut len = data->blocks * data->blocksize;
22907133f2eSMarek Vasut
23007133f2eSMarek Vasut while (len) {
23107133f2eSMarek Vasut /* The controller is ready to receive data */
23207133f2eSMarek Vasut if (readl(®s->i_reg) & MMC_I_REG_TXFIFO_WR_REQ) {
233b4141195SMasahiro Yamada size = min(len, (uint32_t)PXAMMC_FIFO_SIZE);
23407133f2eSMarek Vasut len -= size;
23507133f2eSMarek Vasut size /= 4;
23607133f2eSMarek Vasut
23707133f2eSMarek Vasut while (size--)
23807133f2eSMarek Vasut writel(*buf++, ®s->txfifo);
23907133f2eSMarek Vasut
240b4141195SMasahiro Yamada if (min(len, (uint32_t)PXAMMC_FIFO_SIZE) < 32)
24107133f2eSMarek Vasut writel(MMC_PRTBUF_BUF_PART_FULL, ®s->prtbuf);
24207133f2eSMarek Vasut }
24307133f2eSMarek Vasut
24407133f2eSMarek Vasut if (readl(®s->stat) & MMC_STAT_ERRORS)
24507133f2eSMarek Vasut return -EIO;
24607133f2eSMarek Vasut }
24707133f2eSMarek Vasut
24807133f2eSMarek Vasut /* Wait for the transmission-done interrupt */
24907133f2eSMarek Vasut ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
25007133f2eSMarek Vasut if (ret)
25107133f2eSMarek Vasut return ret;
25207133f2eSMarek Vasut
25307133f2eSMarek Vasut /* Wait until the data are really written to the card */
25407133f2eSMarek Vasut ret = pxa_mmc_wait(mmc, MMC_STAT_PRG_DONE);
25507133f2eSMarek Vasut if (ret)
25607133f2eSMarek Vasut return ret;
25707133f2eSMarek Vasut
25807133f2eSMarek Vasut return 0;
25907133f2eSMarek Vasut }
26007133f2eSMarek Vasut
pxa_mmc_request(struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)26107133f2eSMarek Vasut static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd,
26207133f2eSMarek Vasut struct mmc_data *data)
26307133f2eSMarek Vasut {
26493bfd616SPantelis Antoniou struct pxa_mmc_priv *priv = mmc->priv;
26507133f2eSMarek Vasut struct pxa_mmc_regs *regs = priv->regs;
26607133f2eSMarek Vasut uint32_t cmdat = 0;
26707133f2eSMarek Vasut int ret;
26807133f2eSMarek Vasut
26907133f2eSMarek Vasut /* Stop the controller */
27007133f2eSMarek Vasut ret = pxa_mmc_stop_clock(mmc);
27107133f2eSMarek Vasut if (ret)
27207133f2eSMarek Vasut return ret;
27307133f2eSMarek Vasut
27407133f2eSMarek Vasut /* If we're doing data transfer, configure the controller accordingly */
27507133f2eSMarek Vasut if (data) {
27607133f2eSMarek Vasut writel(data->blocks, ®s->nob);
27707133f2eSMarek Vasut writel(data->blocksize, ®s->blklen);
27807133f2eSMarek Vasut /* This delay can be optimized, but stick with max value */
27907133f2eSMarek Vasut writel(0xffff, ®s->rdto);
28007133f2eSMarek Vasut cmdat |= MMC_CMDAT_DATA_EN;
28107133f2eSMarek Vasut if (data->flags & MMC_DATA_WRITE)
28207133f2eSMarek Vasut cmdat |= MMC_CMDAT_WRITE;
28307133f2eSMarek Vasut }
28407133f2eSMarek Vasut
28507133f2eSMarek Vasut /* Run in 4bit mode if the card can do it */
28607133f2eSMarek Vasut if (mmc->bus_width == 4)
28707133f2eSMarek Vasut cmdat |= MMC_CMDAT_SD_4DAT;
28807133f2eSMarek Vasut
28907133f2eSMarek Vasut /* Execute the command */
29007133f2eSMarek Vasut ret = pxa_mmc_start_cmd(mmc, cmd, cmdat);
29107133f2eSMarek Vasut if (ret)
29207133f2eSMarek Vasut return ret;
29307133f2eSMarek Vasut
29407133f2eSMarek Vasut /* Wait until the command completes */
29507133f2eSMarek Vasut ret = pxa_mmc_wait(mmc, MMC_STAT_END_CMD_RES);
29607133f2eSMarek Vasut if (ret)
29707133f2eSMarek Vasut return ret;
29807133f2eSMarek Vasut
29907133f2eSMarek Vasut /* Read back the result */
30007133f2eSMarek Vasut ret = pxa_mmc_cmd_done(mmc, cmd);
30107133f2eSMarek Vasut if (ret)
30207133f2eSMarek Vasut return ret;
30307133f2eSMarek Vasut
30407133f2eSMarek Vasut /* In case there was a data transfer scheduled, do it */
30507133f2eSMarek Vasut if (data) {
30607133f2eSMarek Vasut if (data->flags & MMC_DATA_WRITE)
30707133f2eSMarek Vasut pxa_mmc_do_write_xfer(mmc, data);
30807133f2eSMarek Vasut else
30907133f2eSMarek Vasut pxa_mmc_do_read_xfer(mmc, data);
31007133f2eSMarek Vasut }
31107133f2eSMarek Vasut
31207133f2eSMarek Vasut return 0;
31307133f2eSMarek Vasut }
31407133f2eSMarek Vasut
pxa_mmc_set_ios(struct mmc * mmc)31507b0b9c0SJaehoon Chung static int pxa_mmc_set_ios(struct mmc *mmc)
31607133f2eSMarek Vasut {
31793bfd616SPantelis Antoniou struct pxa_mmc_priv *priv = mmc->priv;
31807133f2eSMarek Vasut struct pxa_mmc_regs *regs = priv->regs;
31907133f2eSMarek Vasut uint32_t tmp;
32007133f2eSMarek Vasut uint32_t pxa_mmc_clock;
32107133f2eSMarek Vasut
32207133f2eSMarek Vasut if (!mmc->clock) {
32307133f2eSMarek Vasut pxa_mmc_stop_clock(mmc);
32407b0b9c0SJaehoon Chung return 0;
32507133f2eSMarek Vasut }
32607133f2eSMarek Vasut
32707133f2eSMarek Vasut /* PXA3xx can do 26MHz with special settings. */
32807133f2eSMarek Vasut if (mmc->clock == 26000000) {
32907133f2eSMarek Vasut writel(0x7, ®s->clkrt);
33007b0b9c0SJaehoon Chung return 0;
33107133f2eSMarek Vasut }
33207133f2eSMarek Vasut
33307133f2eSMarek Vasut /* Set clock to the card the usual way. */
33407133f2eSMarek Vasut pxa_mmc_clock = 0;
33593bfd616SPantelis Antoniou tmp = mmc->cfg->f_max / mmc->clock;
33607133f2eSMarek Vasut tmp += tmp % 2;
33707133f2eSMarek Vasut
33807133f2eSMarek Vasut while (tmp > 1) {
33907133f2eSMarek Vasut pxa_mmc_clock++;
34007133f2eSMarek Vasut tmp >>= 1;
34107133f2eSMarek Vasut }
34207133f2eSMarek Vasut
34307133f2eSMarek Vasut writel(pxa_mmc_clock, ®s->clkrt);
34407b0b9c0SJaehoon Chung
34507b0b9c0SJaehoon Chung return 0;
34607133f2eSMarek Vasut }
34707133f2eSMarek Vasut
pxa_mmc_init(struct mmc * mmc)34807133f2eSMarek Vasut static int pxa_mmc_init(struct mmc *mmc)
34907133f2eSMarek Vasut {
35093bfd616SPantelis Antoniou struct pxa_mmc_priv *priv = mmc->priv;
35107133f2eSMarek Vasut struct pxa_mmc_regs *regs = priv->regs;
35207133f2eSMarek Vasut
35307133f2eSMarek Vasut /* Make sure the clock are stopped */
35407133f2eSMarek Vasut pxa_mmc_stop_clock(mmc);
35507133f2eSMarek Vasut
35607133f2eSMarek Vasut /* Turn off SPI mode */
35707133f2eSMarek Vasut writel(0, ®s->spi);
35807133f2eSMarek Vasut
35907133f2eSMarek Vasut /* Set up maximum timeout to wait for command response */
36007133f2eSMarek Vasut writel(MMC_RES_TO_MAX_MASK, ®s->resto);
36107133f2eSMarek Vasut
36207133f2eSMarek Vasut /* Mask all interrupts */
36307133f2eSMarek Vasut writel(~(MMC_I_MASK_TXFIFO_WR_REQ | MMC_I_MASK_RXFIFO_RD_REQ),
36407133f2eSMarek Vasut ®s->i_mask);
36507133f2eSMarek Vasut return 0;
36607133f2eSMarek Vasut }
36707133f2eSMarek Vasut
368ab769f22SPantelis Antoniou static const struct mmc_ops pxa_mmc_ops = {
369ab769f22SPantelis Antoniou .send_cmd = pxa_mmc_request,
370ab769f22SPantelis Antoniou .set_ios = pxa_mmc_set_ios,
371ab769f22SPantelis Antoniou .init = pxa_mmc_init,
372ab769f22SPantelis Antoniou };
373ab769f22SPantelis Antoniou
37493bfd616SPantelis Antoniou static struct mmc_config pxa_mmc_cfg = {
37593bfd616SPantelis Antoniou .name = "PXA MMC",
37693bfd616SPantelis Antoniou .ops = &pxa_mmc_ops,
37793bfd616SPantelis Antoniou .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
37893bfd616SPantelis Antoniou .f_max = PXAMMC_MAX_SPEED,
37993bfd616SPantelis Antoniou .f_min = PXAMMC_MIN_SPEED,
38093bfd616SPantelis Antoniou .host_caps = PXAMMC_HOST_CAPS,
38193bfd616SPantelis Antoniou .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
38293bfd616SPantelis Antoniou };
38393bfd616SPantelis Antoniou
pxa_mmc_register(int card_index)38407133f2eSMarek Vasut int pxa_mmc_register(int card_index)
38507133f2eSMarek Vasut {
38607133f2eSMarek Vasut struct mmc *mmc;
38707133f2eSMarek Vasut struct pxa_mmc_priv *priv;
38807133f2eSMarek Vasut uint32_t reg;
38907133f2eSMarek Vasut int ret = -ENOMEM;
39007133f2eSMarek Vasut
39107133f2eSMarek Vasut priv = malloc(sizeof(struct pxa_mmc_priv));
39207133f2eSMarek Vasut if (!priv)
39393bfd616SPantelis Antoniou goto err0;
39493bfd616SPantelis Antoniou
39593bfd616SPantelis Antoniou memset(priv, 0, sizeof(*priv));
39607133f2eSMarek Vasut
39707133f2eSMarek Vasut switch (card_index) {
39807133f2eSMarek Vasut case 0:
39907133f2eSMarek Vasut priv->regs = (struct pxa_mmc_regs *)MMC0_BASE;
40007133f2eSMarek Vasut break;
40107133f2eSMarek Vasut case 1:
40207133f2eSMarek Vasut priv->regs = (struct pxa_mmc_regs *)MMC1_BASE;
40307133f2eSMarek Vasut break;
40407133f2eSMarek Vasut default:
40593bfd616SPantelis Antoniou ret = -EINVAL;
40607133f2eSMarek Vasut printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n",
40707133f2eSMarek Vasut card_index);
40893bfd616SPantelis Antoniou goto err1;
40907133f2eSMarek Vasut }
41007133f2eSMarek Vasut
41107133f2eSMarek Vasut #ifndef CONFIG_CPU_MONAHANS /* PXA2xx */
41207133f2eSMarek Vasut reg = readl(CKEN);
41307133f2eSMarek Vasut reg |= CKEN12_MMC;
41407133f2eSMarek Vasut writel(reg, CKEN);
41507133f2eSMarek Vasut #else /* PXA3xx */
41607133f2eSMarek Vasut reg = readl(CKENA);
41707133f2eSMarek Vasut reg |= CKENA_12_MMC0 | CKENA_13_MMC1;
41807133f2eSMarek Vasut writel(reg, CKENA);
41907133f2eSMarek Vasut #endif
42007133f2eSMarek Vasut
42193bfd616SPantelis Antoniou mmc = mmc_create(&pxa_mmc_cfg, priv);
42293bfd616SPantelis Antoniou if (mmc == NULL)
42393bfd616SPantelis Antoniou goto err1;
42407133f2eSMarek Vasut
42507133f2eSMarek Vasut return 0;
42607133f2eSMarek Vasut
42707133f2eSMarek Vasut err1:
42893bfd616SPantelis Antoniou free(priv);
42907133f2eSMarek Vasut err0:
43007133f2eSMarek Vasut return ret;
43107133f2eSMarek Vasut }
432