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/openbmc/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2x00config.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
24 struct rt2x00intf_conf conf; in rt2x00lib_config_intf() local
27 conf.type = type; in rt2x00lib_config_intf()
31 conf.sync = TSF_SYNC_ADHOC; in rt2x00lib_config_intf()
35 conf.sync = TSF_SYNC_AP_NONE; in rt2x00lib_config_intf()
38 conf.sync = TSF_SYNC_INFRA; in rt2x00lib_config_intf()
41 conf.sync = TSF_SYNC_NONE; in rt2x00lib_config_intf()
51 memset(conf.mac, 0, sizeof(conf.mac)); in rt2x00lib_config_intf()
53 memcpy(conf.mac, mac, ETH_ALEN); in rt2x00lib_config_intf()
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/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm016-dc2 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
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H A Dzynqmp-zcu104-revC.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
38 stdout-path = "serial0:115200n8";
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H A Dzynqmp-zcu104-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
38 stdout-path = "serial0:115200n8";
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H A Dzynqmp-sck-kv-g-revB.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 /dts-v1/;
20 si5332_0: si5332-0 { /* u17 */
21 compatible = "fixed-clock";
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H A Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 model = "ZynqMP zc1751-xm015-dc1 RevA";
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H A Dzynqmp-sck-kv-g-revA.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
9 * "A" - A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interposer
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/net/ti-dp83867.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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H A Dzynqmp-zc1751-xm019-dc5.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm019-dc5 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
33 stdout-path = "serial0:115200n8";
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H A Dzynqmp-zcu100-revC.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
12 /dts-v1/;
15 #include "zynqmp-clk-ccf.dtsi"
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
18 #include <dt-bindings/gpio/gpio.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 #include <dt-bindings/phy/phy.h>
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/openbmc/linux/drivers/isdn/mISDN/
H A Ddsp_cmx.c20 * There are 3 different solutions: -1 = software, 0 = hardware-crossconnect
21 * 1-n = hardware-conference. The n will give the conference number.
39 * - Crossconnecting or even conference, if more than two members are together.
40 * - Force mixing of transmit data with other crossconnect/conference members.
41 * - Echo generation to benchmark the delay of audio processing.
42 * - Use hardware to minimize cpu load, disable FIFO load and minimize delay.
43 * - Dejittering and clock generation.
48 * RX-Buffer
51 * ----------------+-------------+-------------------
53 * The rx-buffer is a ring buffer used to store the received data for each
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/openbmc/linux/drivers/net/wireless/ti/wlcore/
H A Dacx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2008-2009 Nokia Corporation
33 ret = -ENOMEM; in wl1271_acx_wake_up_conditions()
37 wake_up->role_id = wlvif->role_id; in wl1271_acx_wake_up_conditions()
38 wake_up->wake_up_event = wake_up_event; in wl1271_acx_wake_up_conditions()
39 wake_up->listen_interval = listen_interval; in wl1271_acx_wake_up_conditions()
62 ret = -ENOMEM; in wl1271_acx_sleep_auth()
66 auth->sleep_auth = sleep_auth; in wl1271_acx_sleep_auth()
75 wl->sleep_auth = sleep_auth; in wl1271_acx_sleep_auth()
91 return -EINVAL; in wl1271_acx_tx_power()
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/openbmc/linux/net/mac80211/
H A Dwpa.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2002-2004, Instant802 Networks, Inc.
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 * Copyright (C) 2020-2022 Intel Corporation
36 struct sk_buff *skb = tx->skb; in ieee80211_tx_h_michael_mic_add()
40 hdr = (struct ieee80211_hdr *)skb->data; in ieee80211_tx_h_michael_mic_add()
41 if (!tx->key || tx->key->conf.cipher != WLAN_CIPHER_SUITE_TKIP || in ieee80211_tx_h_michael_mic_add()
42 skb->len < 24 || !ieee80211_is_data_present(hdr->frame_control)) in ieee80211_tx_h_michael_mic_add()
45 hdrlen = ieee80211_hdrlen(hdr->frame_control); in ieee80211_tx_h_michael_mic_add()
46 if (skb->len < hdrlen) in ieee80211_tx_h_michael_mic_add()
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H A Dwep.c1 // SPDX-License-Identifier: GPL-2.0-only
28 get_random_bytes(&local->wep_iv, IEEE80211_WEP_IV_LEN); in ieee80211_wep_init()
50 local->wep_iv++; in ieee80211_wep_get_iv()
51 if (ieee80211_wep_weak_iv(local->wep_iv, keylen)) in ieee80211_wep_get_iv()
52 local->wep_iv += 0x0100; in ieee80211_wep_get_iv()
57 *iv++ = (local->wep_iv >> 16) & 0xff; in ieee80211_wep_get_iv()
58 *iv++ = (local->wep_iv >> 8) & 0xff; in ieee80211_wep_get_iv()
59 *iv++ = local->wep_iv & 0xff; in ieee80211_wep_get_iv()
68 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; in ieee80211_wep_add_iv()
73 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PROTECTED); in ieee80211_wep_add_iv()
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/openbmc/qemu/hw/net/
H A Dstellaris_enet.c12 #include "hw/qdev-properties.h"
78 StellarisEnetRxFrame rx[31]; member
82 NICConf conf; member
106 if (s->next_packet >= ARRAY_SIZE(s->rx)) { in stellaris_enet_post_load()
107 return -1; in stellaris_enet_post_load()
110 if (s->np > ARRAY_SIZE(s->rx)) { in stellaris_enet_post_load()
111 return -1; in stellaris_enet_post_load()
114 for (i = 0; i < ARRAY_SIZE(s->rx); i++) { in stellaris_enet_post_load()
115 if (s->rx[i].len > ARRAY_SIZE(s->rx[i].data)) { in stellaris_enet_post_load()
116 return -1; in stellaris_enet_post_load()
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H A Dxgmac.c4 * derived from the Xilinx AXI-Ethernet by Edgar E. Iglesias.
29 #include "hw/qdev-properties.h"
62 /* Remote Wake-Up Frame Filter */
84 #define DMA_CUR_RX_DESC_ADDR 0x000003d3 /* Current Host Rx Descriptor */
86 #define DMA_CUR_RX_BUF_ADDR 0x000003d5 /* Current Host Rx Buffer */
93 #define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
94 #define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
118 #define DMA_CONTROL_DFF 0x01000000 /* Disable flush of rx frames */
136 uint64_t rx; member
152 NICConf conf; member
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/openbmc/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_cn9k_pf.c1 // SPDX-License-Identifier: GPL-2.0
22 /* Names of Hardware non-queue generic interrupts */
45 struct device *dev = &oct->pdev->dev; in cn93_dump_regs()
47 dev_info(dev, "IQ-%d register dump\n", qno); in cn93_dump_regs()
76 dev_info(dev, "OQ-%d register dump\n", qno); in cn93_dump_regs()
112 struct octep_config *conf = oct->conf; in cn93_reset_iq() local
115 dev_dbg(&oct->pdev->dev, "Reset PF IQ-%d\n", q_no); in cn93_reset_iq()
118 q_no += conf->pf_ring_cfg.srn; in cn93_reset_iq()
137 /* Reset Hardware Rx queue */
142 q_no += CFG_GET_PORTS_PF_SRN(oct->conf); in cn93_reset_oq()
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H A Doctep_main.c1 // SPDX-License-Identifier: GPL-2.0
36 * octep_alloc_ioq_vectors() - Allocate Tx/Rx Queue interrupt info.
40 * Allocate resources to hold per Tx/Rx queue interrupt info.
42 * is scheduled and includes quick access to private data of Tx/Rx queue
46 * -1, if failed to allocate any resource.
53 for (i = 0; i < oct->num_oqs; i++) { in octep_alloc_ioq_vectors()
54 oct->ioq_vector[i] = vzalloc(sizeof(*oct->ioq_vector[i])); in octep_alloc_ioq_vectors()
55 if (!oct->ioq_vector[i]) in octep_alloc_ioq_vectors()
58 ioq_vector = oct->ioq_vector[i]; in octep_alloc_ioq_vectors()
59 ioq_vector->iq = oct->iq[i]; in octep_alloc_ioq_vectors()
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/openbmc/u-boot/arch/arm/dts/
H A Dzynq-zc702.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2011 - 2015 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
28 stdout-path = "serial0:115200n8";
31 gpio-keys {
32 compatible = "gpio-keys";
38 wakeup-source;
45 wakeup-source;
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H A Dzynq-zc706.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2011 - 2015 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
28 stdout-path = "serial0:115200n8";
32 compatible = "usb-nop-xceiv";
33 #phy-cells = <0>;
38 ps-clk-frequency = <33333333>;
43 phy-mode = "rgmii-id";
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/openbmc/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-zc702.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
12 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
28 stdout-path = "serial0:115200n8";
31 gpio-keys {
32 compatible = "gpio-keys";
34 switch-14 {
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H A Dzynq-zc706.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
27 stdout-path = "serial0:115200n8";
31 compatible = "usb-nop-xceiv";
32 #phy-cells = <0>;
37 ps-clk-frequency = <33333333>;
42 phy-mode = "rgmii-id";
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/openbmc/linux/drivers/spi/
H A Dspi-ep93xx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Mika Westerberg
7 * Explicit FIFO handling code was inspired by amba-pl022 driver.
9 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
30 #include <linux/platform_data/dma-ep93xx.h>
31 #include <linux/platform_data/spi-ep93xx.h>
65 /* maximum depth of RX/TX FIFO */
69 * struct ep93xx_spi - EP93xx SPI controller structure
74 * @rx: current byte in transfer to receive
75 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
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H A Dspi-meson-spicc.c7 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/clk-provider.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
71 #define SPICC_RR_EN BIT(3) /* RX FIFO Ready Interrupt */
72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
73 #define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */
74 #define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */
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/openbmc/linux/drivers/tty/serial/
H A Dmax3100.c1 // SPDX-License-Identifier: GPL-2.0+
8 * writing conf clears FIFO buffer and we cannot have this interrupt
29 * The initial minor number is 209 in the low-density serial port:
104 int conf; /* configuration for the MAX31000 member
105 * (bits 0-7, bits 8-11 are irqs) */
114 int rx_enabled; /* if we should rx chars */
146 if (s->parity & MAX3100_PARITY_ODD) in max3100_do_parity()
151 if (s->parity & MAX3100_7BIT) in max3100_do_parity()
167 if (s->parity & MAX3100_7BIT) in max3100_calc_parity()
172 if (s->parity & MAX3100_PARITY_ON) in max3100_calc_parity()
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/openbmc/linux/drivers/net/wireless/ti/wl18xx/
H A Ddebugfs.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2011-2012 Texas Instruments
83 WL18XX_DEBUGFS_FWSTATS_FILE(rx, rx_beacon_early_term, "%u");
84 WL18XX_DEBUGFS_FWSTATS_FILE(rx, rx_out_of_mpdu_nodes, "%u");
85 WL18XX_DEBUGFS_FWSTATS_FILE(rx, rx_hdr_overflow, "%u");
86 WL18XX_DEBUGFS_FWSTATS_FILE(rx, rx_dropped_frame, "%u");
87 WL18XX_DEBUGFS_FWSTATS_FILE(rx, rx_done, "%u");
88 WL18XX_DEBUGFS_FWSTATS_FILE(rx, rx_defrag, "%u");
89 WL18XX_DEBUGFS_FWSTATS_FILE(rx, rx_defrag_end, "%u");
90 WL18XX_DEBUGFS_FWSTATS_FILE(rx, rx_cmplt, "%u");
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