4  * derived from the Xilinx AXI-Ethernet by Edgar E. Iglesias.
29 #include "hw/qdev-properties.h"
62 /* Remote Wake-Up Frame Filter */
84 #define DMA_CUR_RX_DESC_ADDR    0x000003d3   /* Current Host Rx Descriptor */
86 #define DMA_CUR_RX_BUF_ADDR     0x000003d5   /* Current Host Rx Buffer */
93 #define DMA_STATUS_EB_TX_ABORT  0x00080000   /* Error Bits - TX Abort */
94 #define DMA_STATUS_EB_RX_ABORT  0x00100000   /* Error Bits - RX Abort */
118 #define DMA_CONTROL_DFF         0x01000000   /* Disable flush of rx frames */
136     uint64_t rx;  member
152     NICConf conf;  member
165         VMSTATE_UINT64(rx, RxTxStats),
183 static void xgmac_read_desc(XgmacState *s, struct desc *d, int rx)  in xgmac_read_desc()  argument
185     uint32_t addr = rx ? s->regs[DMA_CUR_RX_DESC_ADDR] :  in xgmac_read_desc()
186         s->regs[DMA_CUR_TX_DESC_ADDR];  in xgmac_read_desc()
190 static void xgmac_write_desc(XgmacState *s, struct desc *d, int rx)  in xgmac_write_desc()  argument
192     int reg = rx ? DMA_CUR_RX_DESC_ADDR : DMA_CUR_TX_DESC_ADDR;  in xgmac_write_desc()
193     uint32_t addr = s->regs[reg];  in xgmac_write_desc()
195     if (!rx && (d->ctl_stat & 0x00200000)) {  in xgmac_write_desc()
196         s->regs[reg] = s->regs[DMA_TX_BASE_ADDR];  in xgmac_write_desc()
197     } else if (rx && (d->buffer1_size & 0x8000)) {  in xgmac_write_desc()
198         s->regs[reg] = s->regs[DMA_RCV_BASE_ADDR];  in xgmac_write_desc()
200         s->regs[reg] += sizeof(*d);  in xgmac_write_desc()
231             DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- "  in xgmac_enet_send()
237             DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- "  in xgmac_enet_send()
255             qemu_send_packet(qemu_get_queue(s->nic), frame, len);  in xgmac_enet_send()
258             s->regs[DMA_STATUS] |= DMA_STATUS_TI | DMA_STATUS_NIS;  in xgmac_enet_send()
268     int stat = s->regs[DMA_STATUS] & s->regs[DMA_INTR_ENA];  in enet_update_irq()
269     qemu_set_irq(s->sbd_irq, !!stat);  in enet_update_irq()
283         if (addr < ARRAY_SIZE(s->regs)) {  in enet_read()
284             r = s->regs[addr];  in enet_read()
299         s->regs[DMA_BUS_MODE] = value & ~0x1;  in enet_write()
305         s->regs[DMA_STATUS] = s->regs[DMA_STATUS] & ~value;  in enet_write()
308         s->regs[DMA_RCV_BASE_ADDR] = s->regs[DMA_CUR_RX_DESC_ADDR] = value;  in enet_write()
311         s->regs[DMA_TX_BASE_ADDR] = s->regs[DMA_CUR_TX_DESC_ADDR] = value;  in enet_write()
314         if (addr < ARRAY_SIZE(s->regs)) {  in enet_write()
315             s->regs[addr] = value;  in enet_write()
330     /* RX enabled?  */  in eth_can_rx()
331     return s->regs[DMA_CONTROL] & DMA_CONTROL_SR;  in eth_can_rx()
344         return -1;  in eth_rx()
350         s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS;  in eth_rx()
351         ret = -1;  in eth_rx()
357         s->regs[DMA_STATUS] |= DMA_STATUS_RU | DMA_STATUS_AIS;  in eth_rx()
369     s->stats.rx_bytes += size;  in eth_rx()
370     s->stats.rx++;  in eth_rx()
372         s->stats.rx_mcast++;  in eth_rx()
374         s->stats.rx_bcast++;  in eth_rx()
377     s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS;  in eth_rx()
396     memory_region_init_io(&s->iomem, OBJECT(s), &enet_mem_ops, s,  in xgmac_enet_realize()
398     sysbus_init_mmio(sbd, &s->iomem);  in xgmac_enet_realize()
399     sysbus_init_irq(sbd, &s->sbd_irq);  in xgmac_enet_realize()
400     sysbus_init_irq(sbd, &s->pmt_irq);  in xgmac_enet_realize()
401     sysbus_init_irq(sbd, &s->mci_irq);  in xgmac_enet_realize()
403     qemu_macaddr_default_if_unset(&s->conf.macaddr);  in xgmac_enet_realize()
404     s->nic = qemu_new_nic(&net_xgmac_enet_info, &s->conf,  in xgmac_enet_realize()
405                           object_get_typename(OBJECT(dev)), dev->id,  in xgmac_enet_realize()
406                           &dev->mem_reentrancy_guard, s);  in xgmac_enet_realize()
407     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);  in xgmac_enet_realize()
409     s->regs[XGMAC_ADDR_HIGH(0)] = (s->conf.macaddr.a[5] << 8) |  in xgmac_enet_realize()
410                                    s->conf.macaddr.a[4];  in xgmac_enet_realize()
411     s->regs[XGMAC_ADDR_LOW(0)] = (s->conf.macaddr.a[3] << 24) |  in xgmac_enet_realize()
412                                  (s->conf.macaddr.a[2] << 16) |  in xgmac_enet_realize()
413                                  (s->conf.macaddr.a[1] << 8) |  in xgmac_enet_realize()
414                                   s->conf.macaddr.a[0];  in xgmac_enet_realize()
418     DEFINE_NIC_PROPERTIES(XgmacState, conf),
426     dc->realize = xgmac_enet_realize;  in xgmac_enet_class_init()
427     dc->vmsd = &vmstate_xgmac;  in xgmac_enet_class_init()